Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 25ad00bb authored by Alan Cox's avatar Alan Cox Committed by Greg Kroah-Hartman
Browse files

Staging: et1310: kill pAdapter in favour of a sane name 



Signed-off-by: default avatarAlan Cox <alan@linux.intel.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@suse.de>
parent 106a47ba

drivers/staging/et131x/et1310_eeprom.c

+7 −7
Original line number Diff line number Diff line
@@ -143,7 +143,7 @@ 


/**

 * EepromWriteByte - Write a byte to the ET1310's EEPROM

 * @pAdapter: pointer to our private adapter structure

 * @etdev: pointer to our private adapter structure

 * @unAddress: the address to write

 * @bData: the value to write

 * @unEepronId: the ID of the EEPROM
@@ -151,11 +151,11 @@ 
 *

 * Returns SUCCESS or FAILURE

 */

int32_t EepromWriteByte(struct et131x_adapter *pAdapter, uint32_t unAddress,

int32_t EepromWriteByte(struct et131x_adapter *etdev, uint32_t unAddress,

			uint8_t bData, uint32_t unEepromId,

			uint32_t unAddressingMode)

{

	struct pci_dev *pdev = pAdapter->pdev;

	struct pci_dev *pdev = etdev->pdev;

	int32_t nIndex;

	int32_t nRetries;

	int32_t nError = false;
@@ -292,7 +292,7 @@ int32_t EepromWriteByte(struct et131x_adapter *pAdapter, uint32_t unAddress, 
		 *	   so we do a blind write for load bug.

		 */

		if (bStatus & LBCIF_STATUS_GENERAL_ERROR

		    && pAdapter->RevisionID == 0) {

		    && etdev->RevisionID == 0) {

			break;

		}
@@ -349,7 +349,7 @@ int32_t EepromWriteByte(struct et131x_adapter *pAdapter, uint32_t unAddress, 


/**

 * EepromReadByte - Read a byte from the ET1310's EEPROM

 * @pAdapter: pointer to our private adapter structure

 * @etdev: pointer to our private adapter structure

 * @unAddress: the address from which to read

 * @pbData: a pointer to a byte in which to store the value of the read

 * @unEepronId: the ID of the EEPROM
@@ -357,11 +357,11 @@ int32_t EepromWriteByte(struct et131x_adapter *pAdapter, uint32_t unAddress, 
 *

 * Returns SUCCESS or FAILURE

 */

int32_t EepromReadByte(struct et131x_adapter *pAdapter, uint32_t unAddress,

int32_t EepromReadByte(struct et131x_adapter *etdev, uint32_t unAddress,

		       uint8_t *pbData, uint32_t unEepromId,

		       uint32_t unAddressingMode)

{

	struct pci_dev *pdev = pAdapter->pdev;

	struct pci_dev *pdev = etdev->pdev;

	int32_t nIndex;

	int32_t nError = 0;

	uint8_t bControl;

drivers/staging/et131x/et1310_jagcore.c

+10 −10
Original line number Diff line number Diff line
@@ -99,27 +99,27 @@ extern dbg_info_t *et131x_dbginfo; 
 * ConfigGlobalRegs - Used to configure the global registers on the JAGCore

 * @pAdpater: pointer to our adapter structure

 */

void ConfigGlobalRegs(struct et131x_adapter *pAdapter)

void ConfigGlobalRegs(struct et131x_adapter *etdev)

{

	struct _GLOBAL_t __iomem *pGbl = &pAdapter->CSRAddress->global;

	struct _GLOBAL_t __iomem *pGbl = &etdev->CSRAddress->global;



	DBG_ENTER(et131x_dbginfo);



	if (pAdapter->RegistryPhyLoopbk == false) {

		if (pAdapter->RegistryJumboPacket < 2048) {

	if (etdev->RegistryPhyLoopbk == false) {

		if (etdev->RegistryJumboPacket < 2048) {

			/* Tx / RxDMA and Tx/Rx MAC interfaces have a 1k word

			 * block of RAM that the driver can split between Tx

			 * and Rx as it desires.  Our default is to split it

			 * 50/50:

			 */

			writel(0, &pGbl->rxq_start_addr.value);

			writel(pAdapter->RegistryRxMemEnd,

			writel(etdev->RegistryRxMemEnd,

			       &pGbl->rxq_end_addr.value);

			writel(pAdapter->RegistryRxMemEnd + 1,

			writel(etdev->RegistryRxMemEnd + 1,

			       &pGbl->txq_start_addr.value);

			writel(INTERNAL_MEM_SIZE - 1,

			       &pGbl->txq_end_addr.value);

		} else if (pAdapter->RegistryJumboPacket < 8192) {

		} else if (etdev->RegistryJumboPacket < 8192) {

			/* For jumbo packets > 2k but < 8k, split 50-50. */

			writel(0, &pGbl->rxq_start_addr.value);

			writel(INTERNAL_MEM_RX_OFFSET,
@@ -171,9 +171,9 @@ void ConfigGlobalRegs(struct et131x_adapter *pAdapter) 


/**

 * ConfigMMCRegs - Used to configure the main memory registers in the JAGCore

 * @pAdapter: pointer to our adapter structure

 * @etdev: pointer to our adapter structure

 */

void ConfigMMCRegs(struct et131x_adapter *pAdapter)

void ConfigMMCRegs(struct et131x_adapter *etdev)

{

	MMC_CTRL_t mmc_ctrl = { 0 };
@@ -188,7 +188,7 @@ void ConfigMMCRegs(struct et131x_adapter *pAdapter) 
	mmc_ctrl.bits.arb_disable = 0x0;

	mmc_ctrl.bits.mmc_enable = 0x1;



	writel(mmc_ctrl.value, &pAdapter->CSRAddress->mmc.mmc_ctrl.value);

	writel(mmc_ctrl.value, &etdev->CSRAddress->mmc.mmc_ctrl.value);



	DBG_LEAVE(et131x_dbginfo);

}

drivers/staging/et131x/et1310_mac.c

+110 −110
Original line number Diff line number Diff line
@@ -101,9 +101,9 @@ extern dbg_info_t *et131x_dbginfo; 
 * ConfigMacRegs1 - Initialize the first part of MAC regs

 * @pAdpater: pointer to our adapter structure

 */

void ConfigMACRegs1(struct et131x_adapter *pAdapter)

void ConfigMACRegs1(struct et131x_adapter *etdev)

{

	struct _MAC_t __iomem *pMac = &pAdapter->CSRAddress->mac;

	struct _MAC_t __iomem *pMac = &etdev->CSRAddress->mac;

	MAC_STATION_ADDR1_t station1;

	MAC_STATION_ADDR2_t station2;

	MAC_IPG_t ipg;
@@ -151,12 +151,12 @@ void ConfigMACRegs1(struct et131x_adapter *pAdapter) 
	 * station address is used for generating and checking pause control

	 * packets.

	 */

	station2.bits.Octet1 = pAdapter->CurrentAddress[0];

	station2.bits.Octet2 = pAdapter->CurrentAddress[1];

	station1.bits.Octet3 = pAdapter->CurrentAddress[2];

	station1.bits.Octet4 = pAdapter->CurrentAddress[3];

	station1.bits.Octet5 = pAdapter->CurrentAddress[4];

	station1.bits.Octet6 = pAdapter->CurrentAddress[5];

	station2.bits.Octet1 = etdev->CurrentAddress[0];

	station2.bits.Octet2 = etdev->CurrentAddress[1];

	station1.bits.Octet3 = etdev->CurrentAddress[2];

	station1.bits.Octet4 = etdev->CurrentAddress[3];

	station1.bits.Octet5 = etdev->CurrentAddress[4];

	station1.bits.Octet6 = etdev->CurrentAddress[5];

	writel(station1.value, &pMac->station_addr_1.value);

	writel(station2.value, &pMac->station_addr_2.value);
@@ -167,7 +167,7 @@ void ConfigMACRegs1(struct et131x_adapter *pAdapter) 
	 * Packets larger than (RegistryJumboPacket) that do not contain a

	 * VLAN ID will be dropped by the Rx function.

	 */

	writel(pAdapter->RegistryJumboPacket + 4, &pMac->max_fm_len.value);

	writel(etdev->RegistryJumboPacket + 4, &pMac->max_fm_len.value);



	/* clear out MAC config reset */

	writel(0, &pMac->cfg1.value);
@@ -179,10 +179,10 @@ void ConfigMACRegs1(struct et131x_adapter *pAdapter) 
 * ConfigMacRegs2 - Initialize the second part of MAC regs

 * @pAdpater: pointer to our adapter structure

 */

void ConfigMACRegs2(struct et131x_adapter *pAdapter)

void ConfigMACRegs2(struct et131x_adapter *etdev)

{

	int32_t delay = 0;

	struct _MAC_t __iomem *pMac = &pAdapter->CSRAddress->mac;

	struct _MAC_t __iomem *pMac = &etdev->CSRAddress->mac;

	MAC_CFG1_t cfg1;

	MAC_CFG2_t cfg2;

	MAC_IF_CTRL_t ifctrl;
@@ -190,12 +190,12 @@ void ConfigMACRegs2(struct et131x_adapter *pAdapter) 


	DBG_ENTER(et131x_dbginfo);



	ctl.value = readl(&pAdapter->CSRAddress->txmac.ctl.value);

	ctl.value = readl(&etdev->CSRAddress->txmac.ctl.value);

	cfg1.value = readl(&pMac->cfg1.value);

	cfg2.value = readl(&pMac->cfg2.value);

	ifctrl.value = readl(&pMac->if_ctrl.value);



	if (pAdapter->uiLinkSpeed == TRUEPHY_SPEED_1000MBPS) {

	if (etdev->uiLinkSpeed == TRUEPHY_SPEED_1000MBPS) {

		cfg2.bits.if_mode = 0x2;

		ifctrl.bits.phy_mode = 0x0;

	} else {
@@ -210,8 +210,8 @@ void ConfigMACRegs2(struct et131x_adapter *pAdapter) 
	/* Set up flow control */

	cfg1.bits.tx_flow = 0x1;



	if ((pAdapter->FlowControl == RxOnly) ||

	    (pAdapter->FlowControl == Both)) {

	if ((etdev->FlowControl == RxOnly) ||

	    (etdev->FlowControl == Both)) {

		cfg1.bits.rx_flow = 0x1;

	} else {

		cfg1.bits.rx_flow = 0x0;
@@ -232,7 +232,7 @@ void ConfigMACRegs2(struct et131x_adapter *pAdapter) 
	 */

	cfg2.bits.len_check = 0x1;



	if (pAdapter->RegistryPhyLoopbk == false) {

	if (etdev->RegistryPhyLoopbk == false) {

		cfg2.bits.pad_crc = 0x1;

		cfg2.bits.crc_enable = 0x1;

	} else {
@@ -241,8 +241,8 @@ void ConfigMACRegs2(struct et131x_adapter *pAdapter) 
	}



	/* 1 - full duplex, 0 - half-duplex */

	cfg2.bits.full_duplex = pAdapter->uiDuplexMode;

	ifctrl.bits.ghd_mode = !pAdapter->uiDuplexMode;

	cfg2.bits.full_duplex = etdev->uiDuplexMode;

	ifctrl.bits.ghd_mode = !etdev->uiDuplexMode;



	writel(ifctrl.value, &pMac->if_ctrl.value);

	writel(cfg2.value, &pMac->cfg2.value);
@@ -262,19 +262,19 @@ void ConfigMACRegs2(struct et131x_adapter *pAdapter) 


	DBG_TRACE(et131x_dbginfo,

		"Speed %d, Dup %d, CFG1 0x%08x, CFG2 0x%08x, if_ctrl 0x%08x\n",

		pAdapter->uiLinkSpeed, pAdapter->uiDuplexMode,

		etdev->uiLinkSpeed, etdev->uiDuplexMode,

		readl(&pMac->cfg1.value), readl(&pMac->cfg2.value),

		readl(&pMac->if_ctrl.value));



	/* Enable TXMAC */

	ctl.bits.txmac_en = 0x1;

	ctl.bits.fc_disable = 0x1;

	writel(ctl.value, &pAdapter->CSRAddress->txmac.ctl.value);

	writel(ctl.value, &etdev->CSRAddress->txmac.ctl.value);



	/* Ready to start the RXDMA/TXDMA engine */

	if (!MP_TEST_FLAG(pAdapter, fMP_ADAPTER_LOWER_POWER)) {

		et131x_rx_dma_enable(pAdapter);

		et131x_tx_dma_enable(pAdapter);

	if (!MP_TEST_FLAG(etdev, fMP_ADAPTER_LOWER_POWER)) {

		et131x_rx_dma_enable(etdev);

		et131x_tx_dma_enable(etdev);

	} else {

		DBG_WARNING(et131x_dbginfo,

			    "Didn't enable Rx/Tx due to low-power mode\n");
@@ -283,9 +283,9 @@ void ConfigMACRegs2(struct et131x_adapter *pAdapter) 
	DBG_LEAVE(et131x_dbginfo);

}



void ConfigRxMacRegs(struct et131x_adapter *pAdapter)

void ConfigRxMacRegs(struct et131x_adapter *etdev)

{

	struct _RXMAC_t __iomem *pRxMac = &pAdapter->CSRAddress->rxmac;

	struct _RXMAC_t __iomem *pRxMac = &etdev->CSRAddress->rxmac;

	RXMAC_WOL_SA_LO_t sa_lo;

	RXMAC_WOL_SA_HI_t sa_hi;

	RXMAC_PF_CTRL_t pf_ctrl = { 0 };
@@ -330,22 +330,22 @@ void ConfigRxMacRegs(struct et131x_adapter *pAdapter) 
	writel(0, &pRxMac->mask4_word3);



	/* Lets setup the WOL Source Address */

	sa_lo.bits.sa3 = pAdapter->CurrentAddress[2];

	sa_lo.bits.sa4 = pAdapter->CurrentAddress[3];

	sa_lo.bits.sa5 = pAdapter->CurrentAddress[4];

	sa_lo.bits.sa6 = pAdapter->CurrentAddress[5];

	sa_lo.bits.sa3 = etdev->CurrentAddress[2];

	sa_lo.bits.sa4 = etdev->CurrentAddress[3];

	sa_lo.bits.sa5 = etdev->CurrentAddress[4];

	sa_lo.bits.sa6 = etdev->CurrentAddress[5];

	writel(sa_lo.value, &pRxMac->sa_lo.value);



	sa_hi.bits.sa1 = pAdapter->CurrentAddress[0];

	sa_hi.bits.sa2 = pAdapter->CurrentAddress[1];

	sa_hi.bits.sa1 = etdev->CurrentAddress[0];

	sa_hi.bits.sa2 = etdev->CurrentAddress[1];

	writel(sa_hi.value, &pRxMac->sa_hi.value);



	/* Disable all Packet Filtering */

	writel(0, &pRxMac->pf_ctrl.value);



	/* Let's initialize the Unicast Packet filtering address */

	if (pAdapter->PacketFilter & ET131X_PACKET_TYPE_DIRECTED) {

		SetupDeviceForUnicast(pAdapter);

	if (etdev->PacketFilter & ET131X_PACKET_TYPE_DIRECTED) {

		SetupDeviceForUnicast(etdev);

		pf_ctrl.bits.filter_uni_en = 1;

	} else {

		writel(0, &pRxMac->uni_pf_addr1.value);
@@ -354,18 +354,18 @@ void ConfigRxMacRegs(struct et131x_adapter *pAdapter) 
	}



	/* Let's initialize the Multicast hash */

	if (pAdapter->PacketFilter & ET131X_PACKET_TYPE_ALL_MULTICAST) {

	if (etdev->PacketFilter & ET131X_PACKET_TYPE_ALL_MULTICAST) {

		pf_ctrl.bits.filter_multi_en = 0;

	} else {

		pf_ctrl.bits.filter_multi_en = 1;

		SetupDeviceForMulticast(pAdapter);

		SetupDeviceForMulticast(etdev);

	}



	/* Runt packet filtering.  Didn't work in version A silicon. */

	pf_ctrl.bits.min_pkt_size = NIC_MIN_PACKET_SIZE + 4;

	pf_ctrl.bits.filter_frag_en = 1;



	if (pAdapter->RegistryJumboPacket > 8192) {

	if (etdev->RegistryJumboPacket > 8192) {

		RXMAC_MCIF_CTRL_MAX_SEG_t mcif_ctrl_max_seg;



		/* In order to transmit jumbo packets greater than 8k, the
@@ -408,7 +408,7 @@ void ConfigRxMacRegs(struct et131x_adapter *pAdapter) 
	 * bit 16: Receive frame truncated.

	 * bit 17: Drop packet enable

	 */

	if (pAdapter->uiLinkSpeed == TRUEPHY_SPEED_100MBPS)

	if (etdev->uiLinkSpeed == TRUEPHY_SPEED_100MBPS)

		writel(0x30038, &pRxMac->mif_ctrl.value);

	else

		writel(0x30030, &pRxMac->mif_ctrl.value);
@@ -425,9 +425,9 @@ void ConfigRxMacRegs(struct et131x_adapter *pAdapter) 
	DBG_LEAVE(et131x_dbginfo);

}



void ConfigTxMacRegs(struct et131x_adapter *pAdapter)

void ConfigTxMacRegs(struct et131x_adapter *etdev)

{

	struct _TXMAC_t __iomem *pTxMac = &pAdapter->CSRAddress->txmac;

	struct _TXMAC_t __iomem *pTxMac = &etdev->CSRAddress->txmac;

	TXMAC_CF_PARAM_t Local;



	DBG_ENTER(et131x_dbginfo);
@@ -436,7 +436,7 @@ void ConfigTxMacRegs(struct et131x_adapter *pAdapter) 
	 * cfpt - control frame pause timer set to 64 (0x40)

	 * cfep - control frame extended pause timer set to 0x0

	 */

	if (pAdapter->FlowControl == None) {

	if (etdev->FlowControl == None) {

		writel(0, &pTxMac->cf_param.value);

	} else {

		Local.bits.cfpt = 0x40;
@@ -447,10 +447,10 @@ void ConfigTxMacRegs(struct et131x_adapter *pAdapter) 
	DBG_LEAVE(et131x_dbginfo);

}



void ConfigMacStatRegs(struct et131x_adapter *pAdapter)

void ConfigMacStatRegs(struct et131x_adapter *etdev)

{

	struct _MAC_STAT_t __iomem *pDevMacStat =

		&pAdapter->CSRAddress->macStat;

		&etdev->CSRAddress->macStat;



	DBG_ENTER(et131x_dbginfo);
@@ -538,50 +538,50 @@ void ConfigMacStatRegs(struct et131x_adapter *pAdapter) 
	DBG_LEAVE(et131x_dbginfo);

}



void ConfigFlowControl(struct et131x_adapter *pAdapter)

void ConfigFlowControl(struct et131x_adapter *etdev)

{

	if (pAdapter->uiDuplexMode == 0) {

		pAdapter->FlowControl = None;

	if (etdev->uiDuplexMode == 0) {

		etdev->FlowControl = None;

	} else {

		char RemotePause, RemoteAsyncPause;



		ET1310_PhyAccessMiBit(pAdapter,

		ET1310_PhyAccessMiBit(etdev,

				      TRUEPHY_BIT_READ, 5, 10, &RemotePause);

		ET1310_PhyAccessMiBit(pAdapter,

		ET1310_PhyAccessMiBit(etdev,

				      TRUEPHY_BIT_READ, 5, 11,

				      &RemoteAsyncPause);



		if ((RemotePause == TRUEPHY_BIT_SET) &&

		    (RemoteAsyncPause == TRUEPHY_BIT_SET)) {

			pAdapter->FlowControl = pAdapter->RegistryFlowControl;

			etdev->FlowControl = etdev->RegistryFlowControl;

		} else if ((RemotePause == TRUEPHY_BIT_SET) &&

			   (RemoteAsyncPause == TRUEPHY_BIT_CLEAR)) {

			if (pAdapter->RegistryFlowControl == Both)

				pAdapter->FlowControl = Both;

			if (etdev->RegistryFlowControl == Both)

				etdev->FlowControl = Both;

			else

				pAdapter->FlowControl = None;

				etdev->FlowControl = None;

		} else if ((RemotePause == TRUEPHY_BIT_CLEAR) &&

			   (RemoteAsyncPause == TRUEPHY_BIT_CLEAR)) {

			pAdapter->FlowControl = None;

			etdev->FlowControl = None;

		} else {/* if (RemotePause == TRUEPHY_CLEAR_BIT &&

			       RemoteAsyncPause == TRUEPHY_SET_BIT) */

			if (pAdapter->RegistryFlowControl == Both)

				pAdapter->FlowControl = RxOnly;

			if (etdev->RegistryFlowControl == Both)

				etdev->FlowControl = RxOnly;

			else

				pAdapter->FlowControl = None;

				etdev->FlowControl = None;

		}

	}

}



/**

 * UpdateMacStatHostCounters - Update the local copy of the statistics

 * @pAdapter: pointer to the adapter structure

 * @etdev: pointer to the adapter structure

 */

void UpdateMacStatHostCounters(struct et131x_adapter *pAdapter)

void UpdateMacStatHostCounters(struct et131x_adapter *etdev)

{

	struct _ce_stats_t *stats = &pAdapter->Stats;

	struct _ce_stats_t *stats = &etdev->Stats;

	struct _MAC_STAT_t __iomem *pDevMacStat =

		&pAdapter->CSRAddress->macStat;

		&etdev->CSRAddress->macStat;



	stats->collisions += readl(&pDevMacStat->TNcl);

	stats->first_collision += readl(&pDevMacStat->TScl);
@@ -603,13 +603,13 @@ void UpdateMacStatHostCounters(struct et131x_adapter *pAdapter) 


/**

 * HandleMacStatInterrupt

 * @pAdapter: pointer to the adapter structure

 * @etdev: pointer to the adapter structure

 *

 * One of the MACSTAT counters has wrapped.  Update the local copy of

 * the statistics held in the adapter structure, checking the "wrap"

 * bit for each counter.

 */

void HandleMacStatInterrupt(struct et131x_adapter *pAdapter)

void HandleMacStatInterrupt(struct et131x_adapter *etdev)

{

	MAC_STAT_REG_1_t Carry1;

	MAC_STAT_REG_2_t Carry2;
@@ -619,11 +619,11 @@ void HandleMacStatInterrupt(struct et131x_adapter *pAdapter) 
	/* Read the interrupt bits from the register(s).  These are Clear On

	 * Write.

	 */

	Carry1.value = readl(&pAdapter->CSRAddress->macStat.Carry1.value);

	Carry2.value = readl(&pAdapter->CSRAddress->macStat.Carry2.value);

	Carry1.value = readl(&etdev->CSRAddress->macStat.Carry1.value);

	Carry2.value = readl(&etdev->CSRAddress->macStat.Carry2.value);



	writel(Carry1.value, &pAdapter->CSRAddress->macStat.Carry1.value);

	writel(Carry2.value, &pAdapter->CSRAddress->macStat.Carry2.value);

	writel(Carry1.value, &etdev->CSRAddress->macStat.Carry1.value);

	writel(Carry2.value, &etdev->CSRAddress->macStat.Carry2.value);



	/* We need to do update the host copy of all the MAC_STAT counters.

	 * For each counter, check it's overflow bit.  If the overflow bit is
@@ -632,40 +632,40 @@ void HandleMacStatInterrupt(struct et131x_adapter *pAdapter) 
	 * block indicates that one of the counters has wrapped.

	 */

	if (Carry1.bits.rfcs)

		pAdapter->Stats.code_violations += COUNTER_WRAP_16_BIT;

		etdev->Stats.code_violations += COUNTER_WRAP_16_BIT;

	if (Carry1.bits.raln)

		pAdapter->Stats.alignment_err += COUNTER_WRAP_12_BIT;

		etdev->Stats.alignment_err += COUNTER_WRAP_12_BIT;

	if (Carry1.bits.rflr)

		pAdapter->Stats.length_err += COUNTER_WRAP_16_BIT;

		etdev->Stats.length_err += COUNTER_WRAP_16_BIT;

	if (Carry1.bits.rfrg)

		pAdapter->Stats.other_errors += COUNTER_WRAP_16_BIT;

		etdev->Stats.other_errors += COUNTER_WRAP_16_BIT;

	if (Carry1.bits.rcde)

		pAdapter->Stats.crc_err += COUNTER_WRAP_16_BIT;

		etdev->Stats.crc_err += COUNTER_WRAP_16_BIT;

	if (Carry1.bits.rovr)

		pAdapter->Stats.rx_ov_flow += COUNTER_WRAP_16_BIT;

		etdev->Stats.rx_ov_flow += COUNTER_WRAP_16_BIT;

	if (Carry1.bits.rdrp)

		pAdapter->Stats.norcvbuf += COUNTER_WRAP_16_BIT;

		etdev->Stats.norcvbuf += COUNTER_WRAP_16_BIT;

	if (Carry2.bits.tovr)

		pAdapter->Stats.max_pkt_error += COUNTER_WRAP_12_BIT;

		etdev->Stats.max_pkt_error += COUNTER_WRAP_12_BIT;

	if (Carry2.bits.tund)

		pAdapter->Stats.tx_uflo += COUNTER_WRAP_12_BIT;

		etdev->Stats.tx_uflo += COUNTER_WRAP_12_BIT;

	if (Carry2.bits.tscl)

		pAdapter->Stats.first_collision += COUNTER_WRAP_12_BIT;

		etdev->Stats.first_collision += COUNTER_WRAP_12_BIT;

	if (Carry2.bits.tdfr)

		pAdapter->Stats.tx_deferred += COUNTER_WRAP_12_BIT;

		etdev->Stats.tx_deferred += COUNTER_WRAP_12_BIT;

	if (Carry2.bits.tmcl)

		pAdapter->Stats.excessive_collisions += COUNTER_WRAP_12_BIT;

		etdev->Stats.excessive_collisions += COUNTER_WRAP_12_BIT;

	if (Carry2.bits.tlcl)

		pAdapter->Stats.late_collisions += COUNTER_WRAP_12_BIT;

		etdev->Stats.late_collisions += COUNTER_WRAP_12_BIT;

	if (Carry2.bits.tncl)

		pAdapter->Stats.collisions += COUNTER_WRAP_12_BIT;

		etdev->Stats.collisions += COUNTER_WRAP_12_BIT;



	DBG_LEAVE(et131x_dbginfo);

}



void SetupDeviceForMulticast(struct et131x_adapter *pAdapter)

void SetupDeviceForMulticast(struct et131x_adapter *etdev)

{

	struct _RXMAC_t __iomem *rxmac = &pAdapter->CSRAddress->rxmac;

	struct _RXMAC_t __iomem *rxmac = &etdev->CSRAddress->rxmac;

	uint32_t nIndex;

	uint32_t result;

	uint32_t hash1 = 0;
@@ -681,24 +681,24 @@ void SetupDeviceForMulticast(struct et131x_adapter *pAdapter) 
	 * specified) then we should pass NO multi-cast addresses to the

	 * driver.

	 */

	if (pAdapter->PacketFilter & ET131X_PACKET_TYPE_MULTICAST) {

	if (etdev->PacketFilter & ET131X_PACKET_TYPE_MULTICAST) {

		DBG_VERBOSE(et131x_dbginfo,

			    "MULTICAST flag is set, MCCount: %d\n",

			    pAdapter->MCAddressCount);

			    etdev->MCAddressCount);



		/* Loop through our multicast array and set up the device */

		for (nIndex = 0; nIndex < pAdapter->MCAddressCount; nIndex++) {

		for (nIndex = 0; nIndex < etdev->MCAddressCount; nIndex++) {

			DBG_VERBOSE(et131x_dbginfo,

			    "MCList[%d]: %02x:%02x:%02x:%02x:%02x:%02x\n",

			    nIndex,

			    pAdapter->MCList[nIndex][0],

			    pAdapter->MCList[nIndex][1],

			    pAdapter->MCList[nIndex][2],

			    pAdapter->MCList[nIndex][3],

			    pAdapter->MCList[nIndex][4],

			    pAdapter->MCList[nIndex][5]);

			    etdev->MCList[nIndex][0],

			    etdev->MCList[nIndex][1],

			    etdev->MCList[nIndex][2],

			    etdev->MCList[nIndex][3],

			    etdev->MCList[nIndex][4],

			    etdev->MCList[nIndex][5]);



			result = ether_crc(6, pAdapter->MCList[nIndex]);

			result = ether_crc(6, etdev->MCList[nIndex]);



			result = (result & 0x3F800000) >> 23;
@@ -718,7 +718,7 @@ void SetupDeviceForMulticast(struct et131x_adapter *pAdapter) 
	}



	/* Write out the new hash to the device */

	pm_csr.value = readl(&pAdapter->CSRAddress->global.pm_csr.value);

	pm_csr.value = readl(&etdev->CSRAddress->global.pm_csr.value);

	if (pm_csr.bits.pm_phy_sw_coma == 0) {

		writel(hash1, &rxmac->multi_hash1);

		writel(hash2, &rxmac->multi_hash2);
@@ -729,9 +729,9 @@ void SetupDeviceForMulticast(struct et131x_adapter *pAdapter) 
	DBG_LEAVE(et131x_dbginfo);

}



void SetupDeviceForUnicast(struct et131x_adapter *pAdapter)

void SetupDeviceForUnicast(struct et131x_adapter *etdev)

{

	struct _RXMAC_t __iomem *rxmac = &pAdapter->CSRAddress->rxmac;

	struct _RXMAC_t __iomem *rxmac = &etdev->CSRAddress->rxmac;

	RXMAC_UNI_PF_ADDR1_t uni_pf1;

	RXMAC_UNI_PF_ADDR2_t uni_pf2;

	RXMAC_UNI_PF_ADDR3_t uni_pf3;
@@ -748,22 +748,22 @@ void SetupDeviceForUnicast(struct et131x_adapter *pAdapter) 
	 * Set up unicast packet filter reg 3 to be the octets 2 - 5 of the

	 * MAC address for first address

	 */

	uni_pf3.bits.addr1_1 = pAdapter->CurrentAddress[0];

	uni_pf3.bits.addr1_2 = pAdapter->CurrentAddress[1];

	uni_pf3.bits.addr2_1 = pAdapter->CurrentAddress[0];

	uni_pf3.bits.addr2_2 = pAdapter->CurrentAddress[1];



	uni_pf2.bits.addr2_3 = pAdapter->CurrentAddress[2];

	uni_pf2.bits.addr2_4 = pAdapter->CurrentAddress[3];

	uni_pf2.bits.addr2_5 = pAdapter->CurrentAddress[4];

	uni_pf2.bits.addr2_6 = pAdapter->CurrentAddress[5];



	uni_pf1.bits.addr1_3 = pAdapter->CurrentAddress[2];

	uni_pf1.bits.addr1_4 = pAdapter->CurrentAddress[3];

	uni_pf1.bits.addr1_5 = pAdapter->CurrentAddress[4];

	uni_pf1.bits.addr1_6 = pAdapter->CurrentAddress[5];



	pm_csr.value = readl(&pAdapter->CSRAddress->global.pm_csr.value);

	uni_pf3.bits.addr1_1 = etdev->CurrentAddress[0];

	uni_pf3.bits.addr1_2 = etdev->CurrentAddress[1];

	uni_pf3.bits.addr2_1 = etdev->CurrentAddress[0];

	uni_pf3.bits.addr2_2 = etdev->CurrentAddress[1];



	uni_pf2.bits.addr2_3 = etdev->CurrentAddress[2];

	uni_pf2.bits.addr2_4 = etdev->CurrentAddress[3];

	uni_pf2.bits.addr2_5 = etdev->CurrentAddress[4];

	uni_pf2.bits.addr2_6 = etdev->CurrentAddress[5];



	uni_pf1.bits.addr1_3 = etdev->CurrentAddress[2];

	uni_pf1.bits.addr1_4 = etdev->CurrentAddress[3];

	uni_pf1.bits.addr1_5 = etdev->CurrentAddress[4];

	uni_pf1.bits.addr1_6 = etdev->CurrentAddress[5];



	pm_csr.value = readl(&etdev->CSRAddress->global.pm_csr.value);

	if (pm_csr.bits.pm_phy_sw_coma == 0) {

		writel(uni_pf1.value, &rxmac->uni_pf_addr1.value);

		writel(uni_pf2.value, &rxmac->uni_pf_addr2.value);

drivers/staging/et131x/et1310_phy.c

+185 −185

File changed.

Preview size limit exceeded, changes collapsed.

drivers/staging/et131x/et1310_pm.c

+23 −23
Original line number Diff line number Diff line
@@ -99,7 +99,7 @@ extern dbg_info_t *et131x_dbginfo; 


/**

 * EnablePhyComa - called when network cable is unplugged

 * @pAdapter: pointer to our adapter structure

 * @etdev: pointer to our adapter structure

 *

 * driver receive an phy status change interrupt while in D0 and check that

 * phy_status is down.
@@ -117,7 +117,7 @@ extern dbg_info_t *et131x_dbginfo; 
 *       indicating linkup status, call the MPDisablePhyComa routine to

 *             restore JAGCore and gigE PHY

 */

void EnablePhyComa(struct et131x_adapter *pAdapter)

void EnablePhyComa(struct et131x_adapter *etdev)

{

	unsigned long lockflags;

	PM_CSR_t GlobalPmCSR;
@@ -125,81 +125,81 @@ void EnablePhyComa(struct et131x_adapter *pAdapter) 


	DBG_ENTER(et131x_dbginfo);



	GlobalPmCSR.value = readl(&pAdapter->CSRAddress->global.pm_csr.value);

	GlobalPmCSR.value = readl(&etdev->CSRAddress->global.pm_csr.value);



	/* Save the GbE PHY speed and duplex modes. Need to restore this

	 * when cable is plugged back in

	 */

	pAdapter->PoMgmt.PowerDownSpeed = pAdapter->AiForceSpeed;

	pAdapter->PoMgmt.PowerDownDuplex = pAdapter->AiForceDpx;

	etdev->PoMgmt.PowerDownSpeed = etdev->AiForceSpeed;

	etdev->PoMgmt.PowerDownDuplex = etdev->AiForceDpx;



	/* Stop sending packets. */

	spin_lock_irqsave(&pAdapter->SendHWLock, lockflags);

	MP_SET_FLAG(pAdapter, fMP_ADAPTER_LOWER_POWER);

	spin_unlock_irqrestore(&pAdapter->SendHWLock, lockflags);

	spin_lock_irqsave(&etdev->SendHWLock, lockflags);

	MP_SET_FLAG(etdev, fMP_ADAPTER_LOWER_POWER);

	spin_unlock_irqrestore(&etdev->SendHWLock, lockflags);



	/* Wait for outstanding Receive packets */

	while ((MP_GET_RCV_REF(pAdapter) != 0) && (LoopCounter-- > 0))

	while ((MP_GET_RCV_REF(etdev) != 0) && (LoopCounter-- > 0))

		mdelay(2);



	/* Gate off JAGCore 3 clock domains */

	GlobalPmCSR.bits.pm_sysclk_gate = 0;

	GlobalPmCSR.bits.pm_txclk_gate = 0;

	GlobalPmCSR.bits.pm_rxclk_gate = 0;

	writel(GlobalPmCSR.value, &pAdapter->CSRAddress->global.pm_csr.value);

	writel(GlobalPmCSR.value, &etdev->CSRAddress->global.pm_csr.value);



	/* Program gigE PHY in to Coma mode */

	GlobalPmCSR.bits.pm_phy_sw_coma = 1;

	writel(GlobalPmCSR.value, &pAdapter->CSRAddress->global.pm_csr.value);

	writel(GlobalPmCSR.value, &etdev->CSRAddress->global.pm_csr.value);



	DBG_LEAVE(et131x_dbginfo);

}



/**

 * DisablePhyComa - Disable the Phy Coma Mode

 * @pAdapter: pointer to our adapter structure

 * @etdev: pointer to our adapter structure

 */

void DisablePhyComa(struct et131x_adapter *pAdapter)

void DisablePhyComa(struct et131x_adapter *etdev)

{

	PM_CSR_t GlobalPmCSR;



	DBG_ENTER(et131x_dbginfo);



	GlobalPmCSR.value = readl(&pAdapter->CSRAddress->global.pm_csr.value);

	GlobalPmCSR.value = readl(&etdev->CSRAddress->global.pm_csr.value);



	/* Disable phy_sw_coma register and re-enable JAGCore clocks */

	GlobalPmCSR.bits.pm_sysclk_gate = 1;

	GlobalPmCSR.bits.pm_txclk_gate = 1;

	GlobalPmCSR.bits.pm_rxclk_gate = 1;

	GlobalPmCSR.bits.pm_phy_sw_coma = 0;

	writel(GlobalPmCSR.value, &pAdapter->CSRAddress->global.pm_csr.value);

	writel(GlobalPmCSR.value, &etdev->CSRAddress->global.pm_csr.value);



	/* Restore the GbE PHY speed and duplex modes;

	 * Reset JAGCore; re-configure and initialize JAGCore and gigE PHY

	 */

	pAdapter->AiForceSpeed = pAdapter->PoMgmt.PowerDownSpeed;

	pAdapter->AiForceDpx = pAdapter->PoMgmt.PowerDownDuplex;

	etdev->AiForceSpeed = etdev->PoMgmt.PowerDownSpeed;

	etdev->AiForceDpx = etdev->PoMgmt.PowerDownDuplex;



	/* Re-initialize the send structures */

	et131x_init_send(pAdapter);

	et131x_init_send(etdev);



	/* Reset the RFD list and re-start RU  */

	et131x_reset_recv(pAdapter);

	et131x_reset_recv(etdev);



	/* Bring the device back to the state it was during init prior to

	 * autonegotiation being complete.  This way, when we get the auto-neg

	 * complete interrupt, we can complete init by calling ConfigMacREGS2.

	 */

	et131x_soft_reset(pAdapter);

	et131x_soft_reset(etdev);



	/* setup et1310 as per the documentation ?? */

	et131x_adapter_setup(pAdapter);

	et131x_adapter_setup(etdev);



	/* Allow Tx to restart */

	MP_CLEAR_FLAG(pAdapter, fMP_ADAPTER_LOWER_POWER);

	MP_CLEAR_FLAG(etdev, fMP_ADAPTER_LOWER_POWER);



	/* Need to re-enable Rx. */

	et131x_rx_dma_enable(pAdapter);

	et131x_rx_dma_enable(etdev);



	DBG_LEAVE(et131x_dbginfo);

}