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Commit 2547476a authored by Andrea Gelmini's avatar Andrea Gelmini Committed by Vineet Gupta
Browse files

Fix typos 



Signed-off-by: default avatarAndrea Gelmini <andrea.gelmini@gelma.net>
Signed-off-by: default avatarVineet Gupta <vgupta@synopsys.com>
parent 1a695a90

arch/arc/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -127,7 +127,7 @@ libs-y += arch/arc/lib/ $(LIBGCC) 


boot		:= arch/arc/boot



#default target for make without any arguements.

#default target for make without any arguments.

KBUILD_IMAGE	:= bootpImage



all:	$(KBUILD_IMAGE)

arch/arc/include/asm/entry-compact.h

+2 −2
Original line number Diff line number Diff line
@@ -76,8 +76,8 @@ 
	 * We need to be a bit more cautious here. What if a kernel bug in

	 * L1 ISR, caused SP to go whaco (some small value which looks like

	 * USER stk) and then we take L2 ISR.

	 * Above brlo alone would treat it as a valid L1-L2 sceanrio

	 * instead of shouting alound

	 * Above brlo alone would treat it as a valid L1-L2 scenario

	 * instead of shouting around

	 * The only feasible way is to make sure this L2 happened in

	 * L1 prelogue ONLY i.e. ilink2 is less than a pre-set marker in

	 * L1 ISR before it switches stack

arch/arc/include/asm/mmu_context.h

+1 −1
Original line number Diff line number Diff line
@@ -83,7 +83,7 @@ static inline void get_new_mmu_context(struct mm_struct *mm) 
		local_flush_tlb_all();



		/*

		 * Above checke for rollover of 8 bit ASID in 32 bit container.

		 * Above check for rollover of 8 bit ASID in 32 bit container.

		 * If the container itself wrapped around, set it to a non zero

		 * "generation" to distinguish from no context

		 */

arch/arc/include/asm/pgtable.h

+1 −1
Original line number Diff line number Diff line
@@ -47,7 +47,7 @@ 
 * Page Tables are purely for Linux VM's consumption and the bits below are

 * suited to that (uniqueness). Hence some are not implemented in the TLB and

 * some have different value in TLB.

 * e.g. MMU v2: K_READ bit is 8 and so is GLOBAL (possible becoz they live in

 * e.g. MMU v2: K_READ bit is 8 and so is GLOBAL (possible because they live in

 *      seperate PD0 and PD1, which combined forms a translation entry)

 *      while for PTE perspective, they are 8 and 9 respectively

 * with MMU v3: Most bits (except SHARED) represent the exact hardware pos

arch/arc/include/asm/processor.h

+1 −1
Original line number Diff line number Diff line
@@ -78,7 +78,7 @@ struct task_struct; 
#define KSTK_ESP(tsk)   (task_pt_regs(tsk)->sp)



/*

 * Where abouts of Task's sp, fp, blink when it was last seen in kernel mode.

 * Where about of Task's sp, fp, blink when it was last seen in kernel mode.

 * Look in process.c for details of kernel stack layout

 */

#define TSK_K_ESP(tsk)		(tsk->thread.ksp)