Commit 252d6aa6 authored Sep 22, 2015 by Paul Burton Committed by Ralf Baechle Nov 11, 2015

MIPS: CM: Fix GCR_Cx_CONFIG PVPE mask

The PVPE (or PVP in >= CM3) field is 10 bits wide, but the mask
previously only covered the bottom 9 bits. Extend the mask to cover all
10 bits of the field.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: James Hogan <james.hogan@imgtec.com>
Cc: Markos Chandras <markos.chandras@imgtec.com>
Patchwork: https://patchwork.linux-mips.org/patch/11206/

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

parent a8c20614

arch/mips/include/asm/mips-cm.h

+1 −1

Original line number	Diff line number	Diff line
		@@ -359,7 +359,7 @@ BUILD_CM_Cx_R_(tcid_8_priority, 0x80)
		#define CM_GCR_Cx_CONFIG_IOCUTYPE_SHF 10
		#define CM_GCR_Cx_CONFIG_IOCUTYPE_MSK (_ULCAST_(0x3) << 10)
		#define CM_GCR_Cx_CONFIG_PVPE_SHF 0
		#define CM_GCR_Cx_CONFIG_PVPE_MSK (_ULCAST_(0x1ff) << 0)
		#define CM_GCR_Cx_CONFIG_PVPE_MSK (_ULCAST_(0x3ff) << 0)

		/* GCR_Cx_OTHER register fields */
		#define CM_GCR_Cx_OTHER_CORENUM_SHF 16