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Commit 24af98c4 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'locking-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull locking updates from Ingo Molnar:
 "So we have a laundry list of locking subsystem changes:

   - continuing barrier API and code improvements

   - futex enhancements

   - atomics API improvements

   - pvqspinlock enhancements: in particular lock stealing and adaptive
     spinning

   - qspinlock micro-enhancements"

* 'locking-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  futex: Allow FUTEX_CLOCK_REALTIME with FUTEX_WAIT op
  futex: Cleanup the goto confusion in requeue_pi()
  futex: Remove pointless put_pi_state calls in requeue()
  futex: Document pi_state refcounting in requeue code
  futex: Rename free_pi_state() to put_pi_state()
  futex: Drop refcount if requeue_pi() acquired the rtmutex
  locking/barriers, arch: Remove ambiguous statement in the smp_store_mb() documentation
  lcoking/barriers, arch: Use smp barriers in smp_store_release()
  locking/cmpxchg, arch: Remove tas() definitions
  locking/pvqspinlock: Queue node adaptive spinning
  locking/pvqspinlock: Allow limited lock stealing
  locking/pvqspinlock: Collect slowpath lock statistics
  sched/core, locking: Document Program-Order guarantees
  locking, sched: Introduce smp_cond_acquire() and use it
  locking/pvqspinlock, x86: Optimize the PV unlock code path
  locking/qspinlock: Avoid redundant read of next pointer
  locking/qspinlock: Prefetch the next node cacheline
  locking/qspinlock: Use _acquire/_release() versions of cmpxchg() & xchg()
  atomics: Add test for atomic operations with _relaxed variants
parents 9061cbe6 337f1304

Documentation/memory-barriers.txt

+2 −2
Original line number Diff line number Diff line
@@ -1673,8 +1673,8 @@ There are some more advanced barrier functions: 
 (*) smp_store_mb(var, value)



     This assigns the value to the variable and then inserts a full memory

     barrier after it, depending on the function.  It isn't guaranteed to

     insert anything more than a compiler barrier in a UP compilation.

     barrier after it.  It isn't guaranteed to insert anything more than a

     compiler barrier in a UP compilation.





 (*) smp_mb__before_atomic();

arch/blackfin/include/asm/cmpxchg.h

+0 −1
Original line number Diff line number Diff line
@@ -128,6 +128,5 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr, 
#endif /* !CONFIG_SMP */



#define xchg(ptr, x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x), (ptr), sizeof(*(ptr))))

#define tas(ptr) ((void)xchg((ptr), 1))



#endif /* __ARCH_BLACKFIN_CMPXCHG__ */

arch/c6x/include/asm/cmpxchg.h

+0 −2
Original line number Diff line number Diff line
@@ -47,8 +47,6 @@ static inline unsigned int __xchg(unsigned int x, volatile void *ptr, int size) 
#define xchg(ptr, x) \

	((__typeof__(*(ptr)))__xchg((unsigned int)(x), (void *) (ptr), \

				    sizeof(*(ptr))))

#define tas(ptr)    xchg((ptr), 1)





#include <asm-generic/cmpxchg-local.h>

arch/frv/include/asm/cmpxchg.h

+0 −2
Original line number Diff line number Diff line
@@ -69,8 +69,6 @@ extern uint32_t __xchg_32(uint32_t i, volatile void *v); 


#endif



#define tas(ptr) (xchg((ptr), 1))



/*****************************************************************************/

/*

 * compare and conditionally exchange value with memory

arch/ia64/include/asm/barrier.h

+1 −1
Original line number Diff line number Diff line
@@ -77,7 +77,7 @@ do { \ 
	___p1;								\

})



#define smp_store_mb(var, value)	do { WRITE_ONCE(var, value); mb(); } while (0)

#define smp_store_mb(var, value) do { WRITE_ONCE(var, value); smp_mb(); } while (0)



/*

 * The group barrier in front of the rsm & ssm are necessary to ensure