Merge "ARM: dts: msm: Add pin control settings for UFS reset on sdm670" (24af1ae9) · Commits · e / devices / android_kernel_fairphone_FP3

arch/arm64/boot/dts/qcom/sdm670-pinctrl.dtsi

+46 −0

Original line number	Diff line number	Diff line
		@@ -21,6 +21,52 @@
		#interrupt-cells = <2>;
		interrupt-parent = <&pdc>;

		ufs_dev_reset_assert: ufs_dev_reset_assert {
		config {
		pins = "ufs_reset";
		bias-pull-down; /* default: pull down */
		/*
		* UFS_RESET driver strengths are having
		* different values/steps compared to typical
		* GPIO drive strengths.
		*
		* Following table clarifies:
		*
		* HDRV value \| UFS_RESET \| Typical GPIO
		* (dec) \| (mA) \| (mA)
		* 0 \| 0.8 \| 2
		* 1 \| 1.55 \| 4
		* 2 \| 2.35 \| 6
		* 3 \| 3.1 \| 8
		* 4 \| 3.9 \| 10
		* 5 \| 4.65 \| 12
		* 6 \| 5.4 \| 14
		* 7 \| 6.15 \| 16
		*
		* POR value for UFS_RESET HDRV is 3 which means
		* 3.1mA and we want to use that. Hence just
		* specify 8mA to "drive-strength" binding and
		* that should result into writing 3 to HDRV
		* field.
		*/
		drive-strength = <8>; /* default: 3.1 mA */
		output-low; /* active low reset */
		};
		};

		ufs_dev_reset_deassert: ufs_dev_reset_deassert {
		config {
		pins = "ufs_reset";
		bias-pull-down; /* default: pull down */
		/*
		* default: 3.1 mA
		* check comments under ufs_dev_reset_assert
		*/
		drive-strength = <8>;
		output-high; /* active low reset */
		};
		};

		/* QUPv3 South SE mappings */
		/* SE 0 pin mappings */
		qupv3_se0_i2c_pins: qupv3_se0_i2c_pins {

+4 −0

Original line number	Diff line number	Diff line
		@@ -1935,6 +1935,10 @@
		qcom,pm-qos-cpu-group-latency-us = <67 67>;
		qcom,pm-qos-default-cpu = <0>;

		pinctrl-names = "dev-reset-assert", "dev-reset-deassert";
		pinctrl-0 = <&ufs_dev_reset_assert>;
		pinctrl-1 = <&ufs_dev_reset_deassert>;

		resets = <&clock_gcc GCC_UFS_PHY_BCR>;
		reset-names = "core_reset";