Loading arch/arm64/boot/dts/qcom/sdm845-sde.dtsi +2 −7 Original line number Diff line number Diff line Loading @@ -14,11 +14,9 @@ mdss_mdp: qcom,mdss_mdp@ae00000 { compatible = "qcom,sde-kms"; reg = <0x0ae00000 0x81d40>, <0x0aeb0000 0x2008>, <0x0aeac000 0xf0>; <0x0aeb0000 0x2008>; reg-names = "mdp_phys", "vbif_phys", "regdma_phys"; "vbif_phys"; clocks = <&clock_gcc GCC_DISP_AHB_CLK>, Loading Loading @@ -181,9 +179,6 @@ /* offsets are relative to "mdp_phys + qcom,sde-off */ qcom,sde-inline-rot-clk-ctrl = <0x2bc 0x8>, <0x2bc 0xc>; qcom,sde-reg-dma-off = <0>; qcom,sde-reg-dma-version = <0x1>; qcom,sde-reg-dma-trigger-off = <0x119c>; qcom,sde-sspp-vig-blocks { qcom,sde-vig-csc-off = <0x1a00>; Loading Loading
arch/arm64/boot/dts/qcom/sdm845-sde.dtsi +2 −7 Original line number Diff line number Diff line Loading @@ -14,11 +14,9 @@ mdss_mdp: qcom,mdss_mdp@ae00000 { compatible = "qcom,sde-kms"; reg = <0x0ae00000 0x81d40>, <0x0aeb0000 0x2008>, <0x0aeac000 0xf0>; <0x0aeb0000 0x2008>; reg-names = "mdp_phys", "vbif_phys", "regdma_phys"; "vbif_phys"; clocks = <&clock_gcc GCC_DISP_AHB_CLK>, Loading Loading @@ -181,9 +179,6 @@ /* offsets are relative to "mdp_phys + qcom,sde-off */ qcom,sde-inline-rot-clk-ctrl = <0x2bc 0x8>, <0x2bc 0xc>; qcom,sde-reg-dma-off = <0>; qcom,sde-reg-dma-version = <0x1>; qcom,sde-reg-dma-trigger-off = <0x119c>; qcom,sde-sspp-vig-blocks { qcom,sde-vig-csc-off = <0x1a00>; Loading