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Commit 241771ef authored by Ingo Molnar's avatar Ingo Molnar
Browse files

performance counters: x86 support 



Implement performance counters for x86 Intel CPUs.

It's simplified right now: the PERFMON CPU feature is assumed,
which is available in Core2 and later Intel CPUs.

The design is flexible to be extended to more CPU types as well.

Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
parent e7bc62b6

arch/x86/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -643,6 +643,7 @@ config X86_UP_IOAPIC 
config X86_LOCAL_APIC

	def_bool y

	depends on X86_64 || (X86_32 && (X86_UP_APIC || (SMP && !X86_VOYAGER) || X86_GENERICARCH))

	select HAVE_PERF_COUNTERS



config X86_IO_APIC

	def_bool y

arch/x86/ia32/ia32entry.S

+2 −1
Original line number Diff line number Diff line
@@ -826,4 +826,5 @@ ia32_sys_call_table: 
	.quad sys_dup3				/* 330 */

	.quad sys_pipe2

	.quad sys_inotify_init1

	.quad sys_perf_counter_open

ia32_syscall_end:

arch/x86/include/asm/hardirq_32.h

+1 −0
Original line number Diff line number Diff line
@@ -9,6 +9,7 @@ typedef struct { 
	unsigned long idle_timestamp;

	unsigned int __nmi_count;	/* arch dependent */

	unsigned int apic_timer_irqs;	/* arch dependent */

	unsigned int apic_perf_irqs;	/* arch dependent */

	unsigned int irq0_irqs;

	unsigned int irq_resched_count;

	unsigned int irq_call_count;

arch/x86/include/asm/hw_irq.h

+2 −0
Original line number Diff line number Diff line
@@ -30,6 +30,8 @@ 
/* Interrupt handlers registered during init_IRQ */

extern void apic_timer_interrupt(void);

extern void error_interrupt(void);

extern void perf_counter_interrupt(void);



extern void spurious_interrupt(void);

extern void thermal_interrupt(void);

extern void reschedule_interrupt(void);

arch/x86/include/asm/intel_arch_perfmon.h

+22 −12
Original line number Diff line number Diff line
@@ -12,12 +12,14 @@ 
#define ARCH_PERFMON_EVENTSEL_OS			  (1 << 17)

#define ARCH_PERFMON_EVENTSEL_USR			  (1 << 16)



#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL	(0x3c)

#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL		      0x3c

#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_UMASK		(0x00 << 8)

#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX (0)

#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX 		 0

#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_PRESENT \

		(1 << (ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX))



#define ARCH_PERFMON_BRANCH_MISSES_RETIRED			 6



union cpuid10_eax {

	struct {

		unsigned int version_id:8;
@@ -28,4 +30,12 @@ union cpuid10_eax { 
	unsigned int full;

};



#ifdef CONFIG_PERF_COUNTERS

extern void init_hw_perf_counters(void);

extern void perf_counters_lapic_init(int nmi);

#else

static inline void init_hw_perf_counters(void)		{ }

static inline void perf_counters_lapic_init(int nmi)	{ }

#endif



#endif /* _ASM_X86_INTEL_ARCH_PERFMON_H */