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Commit 23eafea6 authored by Sagar Arun Kamble's avatar Sagar Arun Kamble Committed by Daniel Vetter
Browse files

drm/i915/bxt: WaGsvDisableTurbo 



Disable Turbo on steppings prior to B0 on BXT due to hangs seen during GT CPD exit.

Change-Id: I50c5c03f59f5ba092db19e17234951d89db42c6c
Signed-off-by: default avatarSagar Arun Kamble <sagar.a.kamble@intel.com>
Reviewed by: Alex Dai <yu.dai@intel.com>.
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 7b403ffb

drivers/gpu/drm/i915/intel_pm.c

+10 −0
Original line number Diff line number Diff line
@@ -4487,6 +4487,10 @@ static void gen6_set_rps(struct drm_device *dev, u8 val) 
{

	struct drm_i915_private *dev_priv = dev->dev_private;



	/* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */

	if (IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0))

		return;



	WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));

	WARN_ON(val > dev_priv->rps.max_freq);

	WARN_ON(val < dev_priv->rps.min_freq);
@@ -4807,6 +4811,12 @@ static void gen9_enable_rps(struct drm_device *dev) 


	gen6_init_rps_frequencies(dev);



	/* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */

	if (IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) {

		intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);

		return;

	}



	/* Program defaults and thresholds for RPS*/

	I915_WRITE(GEN6_RC_VIDEO_FREQ,

		GEN9_FREQUENCY(dev_priv->rps.rp1_freq));