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Commit 23e89292 authored by Olof Johansson's avatar Olof Johansson
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Merge tag 'tegra-for-3.17-fuse-move' of... 

Merge tag 'tegra-for-3.17-fuse-move' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/cleanup

Merge "ARM: tegra: move fuse code out of arch/arm" from Thierry Reding:

This branch moves code related to the Tegra fuses out of arch/arm and
into a centralized location which could be shared with ARM64. It also
adds support for reading the fuse data through sysfs.

Included is also some preparatory work that moves Tegra-related header
files from include/linux to include/soc/tegra as suggested by Arnd.

Furthermore the Tegra chip ID is now retrieved using a function rather
than a variable so that sanity checks can be done. This is convenient
in subsequent patches that will move some of the code that's currently
called from Tegra machine setup into regular initcalls so that it can
be reused on 64-bit ARM. The sanity checks help with verifying that no
code tries to obtain the Tegra chip ID before the underlying driver is
properly initialized.

* tag 'tegra-for-3.17-fuse-move' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux

:
  soc/tegra: fuse: fix dummy functions
  soc/tegra: fuse: move APB DMA into Tegra20 fuse driver
  soc/tegra: Add efuse and apbmisc bindings
  soc/tegra: Add efuse driver for Tegra
  ARM: tegra: move fuse exports to soc/tegra/fuse.h
  ARM: tegra: export apb dma readl/writel
  ARM: tegra: Use a function to get the chip ID
  ARM: tegra: Sort includes alphabetically
  ARM: tegra: Move includes to include/soc/tegra

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 4cfab57e 2fa937a7

Documentation/ABI/testing/sysfs-driver-tegra-fuse

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What:		/sys/devices/*/<our-device>/fuse

Date:		February 2014

Contact:	Peter De Schrijver <pdeschrijver@nvidia.com>

Description:	read-only access to the efuses on Tegra20, Tegra30, Tegra114

		and Tegra124 SoC's from NVIDIA. The efuses contain write once

		data programmed at the factory. The data is layed out in 32bit

		words in LSB first format. Each bit represents a single value

		as decoded from the fuse registers. Bits order/assignment

		exactly matches the HW registers, including any unused bits.

Users:		any user space application which wants to read the efuses on

		Tegra SoC's

Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.txt

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NVIDIA Tegra20/Tegra30/Tegr114/Tegra124 fuse block.



Required properties:

- compatible : should be:

	"nvidia,tegra20-efuse"

	"nvidia,tegra30-efuse"

	"nvidia,tegra114-efuse"

	"nvidia,tegra124-efuse"

  Details:

  nvidia,tegra20-efuse: Tegra20 requires using APB DMA to read the fuse data

	due to a hardware bug. Tegra20 also lacks certain information which is

	available in later generations such as fab code, lot code, wafer id,..

  nvidia,tegra30-efuse, nvidia,tegra114-efuse and nvidia,tegra124-efuse:

	The differences between these SoCs are the size of the efuse array,

	the location of the spare (OEM programmable) bits and the location of

	the speedo data.

- reg: Should contain 1 entry: the entry gives the physical address and length

       of the fuse registers.

- clocks: Must contain an entry for each entry in clock-names.

  See ../clocks/clock-bindings.txt for details.

- clock-names: Must include the following entries:

  - fuse

- resets: Must contain an entry for each entry in reset-names.

  See ../reset/reset.txt for details.

- reset-names: Must include the following entries:

 - fuse



Example:



	fuse@7000f800 {

		compatible = "nvidia,tegra20-efuse";

		reg = <0x7000F800 0x400>,

		      <0x70000000 0x400>;

		clocks = <&tegra_car TEGRA20_CLK_FUSE>;

		clock-names = "fuse";

		resets = <&tegra_car 39>;

		reset-names = "fuse";

	};

Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt

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NVIDIA Tegra20/Tegra30/Tegr114/Tegra124 apbmisc block



Required properties:

- compatible : should be:

       "nvidia,tegra20-apbmisc"

       "nvidia,tegra30-apbmisc"

       "nvidia,tegra114-apbmisc"

       "nvidia,tegra124-apbmisc"

- reg: Should contain 2 entries: the first entry gives the physical address

       and length of the registers which contain revision and debug features.

       The second entry gives the physical address and length of the

       registers indicating the strapping options.

arch/arm/boot/dts/tegra114.dtsi

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@@ -220,6 +220,12 @@ 
		interrupt-controller;

	};



	apbmisc@70000800 {

		compatible = "nvidia,tegra114-apbmisc", "nvidia,tegra20-apbmisc";

		reg = <0x70000800 0x64   /* Chip revision */

		       0x70000008 0x04>; /* Strapping options */

	};



	pinmux: pinmux@70000868 {

		compatible = "nvidia,tegra114-pinmux";

		reg = <0x70000868 0x148		/* Pad control registers */
@@ -485,6 +491,15 @@ 
		clock-names = "pclk", "clk32k_in";

	};



	fuse@7000f800 {

		compatible = "nvidia,tegra114-efuse";

		reg = <0x7000f800 0x400>;

		clocks = <&tegra_car TEGRA114_CLK_FUSE>;

		clock-names = "fuse";

		resets = <&tegra_car 39>;

		reset-names = "fuse";

	};



	iommu@70019010 {

		compatible = "nvidia,tegra114-smmu", "nvidia,tegra30-smmu";

		reg = <0x70019010 0x02c

arch/arm/boot/dts/tegra124.dtsi

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@@ -179,6 +179,12 @@ 
		#dma-cells = <1>;

	};



	apbmisc@0,70000800 {

		compatible = "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc";

		reg = <0x0 0x70000800 0x0 0x64>,   /* Chip revision */

		      <0x0 0x7000E864 0x0 0x04>;   /* Strapping options */

	};



	pinmux: pinmux@0,70000868 {

		compatible = "nvidia,tegra124-pinmux";

		reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */
@@ -449,6 +455,15 @@ 
		clock-names = "pclk", "clk32k_in";

	};



	fuse@0,7000f800 {

		compatible = "nvidia,tegra124-efuse";

		reg = <0x0 0x7000f800 0x0 0x400>;

		clocks = <&tegra_car TEGRA124_CLK_FUSE>;

		clock-names = "fuse";

		resets = <&tegra_car 39>;

		reset-names = "fuse";

	};



	sdhci@0,700b0000 {

		compatible = "nvidia,tegra124-sdhci";

		reg = <0x0 0x700b0000 0x0 0x200>;