Merge branch 'for-4.3/clk' into for-4.3/dt

NVIDIA Tegra124 DFLL FCPU clocksource

This binding uses the common clock binding:

Documentation/devicetree/bindings/clock/clock-bindings.txt

The DFLL IP block on Tegra is a root clocksource designed for clocking

the fast CPU cluster. It consists of a free-running voltage controlled

oscillator connected to the CPU voltage rail (VDD_CPU), and a closed loop

control module that will automatically adjust the VDD_CPU voltage by

communicating with an off-chip PMIC either via an I2C bus or via PWM signals.

Currently only the I2C mode is supported by these bindings.

Required properties:

- compatible : should be "nvidia,tegra124-dfll"

- reg : Defines the following set of registers, in the order listed:

        - registers for the DFLL control logic.

        - registers for the I2C output logic.

        - registers for the integrated I2C master controller.

        - look-up table RAM for voltage register values.

- interrupts: Should contain the DFLL block interrupt.

- clocks: Must contain an entry for each entry in clock-names.

  See clock-bindings.txt for details.

- clock-names: Must include the following entries:

  - soc: Clock source for the DFLL control logic.

  - ref: The closed loop reference clock

  - i2c: Clock source for the integrated I2C master.

- resets: Must contain an entry for each entry in reset-names.

  See ../reset/reset.txt for details.

- reset-names: Must include the following entries:

  - dvco: Reset control for the DFLL DVCO.

- #clock-cells: Must be 0.

- clock-output-names: Name of the clock output.

- vdd-cpu-supply: Regulator for the CPU voltage rail that the DFLL

  hardware will start controlling. The regulator will be queried for

  the I2C register, control values and supported voltages.

Required properties for the control loop parameters:

- nvidia,sample-rate: Sample rate of the DFLL control loop.

- nvidia,droop-ctrl: See the register CL_DVFS_DROOP_CTRL in the TRM.

- nvidia,force-mode: See the field DFLL_PARAMS_FORCE_MODE in the TRM.

- nvidia,cf: Numeric value, see the field DFLL_PARAMS_CF_PARAM in the TRM.

- nvidia,ci: Numeric value, see the field DFLL_PARAMS_CI_PARAM in the TRM.

- nvidia,cg: Numeric value, see the field DFLL_PARAMS_CG_PARAM in the TRM.

Optional properties for the control loop parameters:

- nvidia,cg-scale: Boolean value, see the field DFLL_PARAMS_CG_SCALE in the TRM.

Required properties for I2C mode:

- nvidia,i2c-fs-rate: I2C transfer rate, if using full speed mode.

Example:

clock@0,70110000 {

        compatible = "nvidia,tegra124-dfll";

        reg = <0 0x70110000 0 0x100>, /* DFLL control */

              <0 0x70110000 0 0x100>, /* I2C output control */

              <0 0x70110100 0 0x100>, /* Integrated I2C controller */

              <0 0x70110200 0 0x100>; /* Look-up table RAM */

        interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;

        clocks = <&tegra_car TEGRA124_CLK_DFLL_SOC>,

                 <&tegra_car TEGRA124_CLK_DFLL_REF>,

                 <&tegra_car TEGRA124_CLK_I2C5>;

        clock-names = "soc", "ref", "i2c";

        resets = <&tegra_car TEGRA124_RST_DFLL_DVCO>;

        reset-names = "dvco";

        #clock-cells = <0>;

        clock-output-names = "dfllCPU_out";

        vdd-cpu-supply = <&vdd_cpu>;

        status = "okay";

        nvidia,sample-rate = <12500>;

        nvidia,droop-ctrl = <0x00000f00>;

        nvidia,force-mode = <1>;

        nvidia,cf = <10>;

        nvidia,ci = <0>;

        nvidia,cg = <2>;

        nvidia,i2c-fs-rate = <400000>;

};

	select HAVE_ARM_SCU if SMP

	select HAVE_ARM_TWD if SMP

	select PINCTRL

	select PM_OPP

	select ARCH_HAS_RESET_CONTROLLER

	select RESET_CONTROLLER

	select SOC_BUS

obj-y					+= clk.o

obj-y					+= clk-audio-sync.o

obj-y					+= clk-dfll.o

obj-y					+= clk-divider.o

obj-y					+= clk-periph.o

obj-y					+= clk-periph-gate.o

obj-$(CONFIG_ARCH_TEGRA_3x_SOC)         += clk-tegra30.o

obj-$(CONFIG_ARCH_TEGRA_114_SOC)	+= clk-tegra114.o

obj-$(CONFIG_ARCH_TEGRA_124_SOC)	+= clk-tegra124.o

obj-$(CONFIG_ARCH_TEGRA_124_SOC)	+= clk-tegra124-dfll-fcpu.o

obj-$(CONFIG_ARCH_TEGRA_132_SOC)	+= clk-tegra124.o

obj-y					+= cvb.o

/*

 * clk-dfll.h - prototypes and macros for the Tegra DFLL clocksource driver

 * Copyright (C) 2013 NVIDIA Corporation.  All rights reserved.

 *

 * Aleksandr Frid <afrid@nvidia.com>

 * Paul Walmsley <pwalmsley@nvidia.com>

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful, but WITHOUT

 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

 * more details.

 */

#ifndef __DRIVERS_CLK_TEGRA_CLK_DFLL_H

#define __DRIVERS_CLK_TEGRA_CLK_DFLL_H

#include <linux/platform_device.h>

#include <linux/reset.h>

#include <linux/types.h>

/**

 * struct tegra_dfll_soc_data - SoC-specific hooks/integration for the DFLL driver

 * @opp_dev: struct device * that holds the OPP table for the DFLL

 * @min_millivolts: minimum voltage (in mV) that the DFLL can operate

 * @tune0_low: DFLL tuning register 0 (low voltage range)

 * @tune0_high: DFLL tuning register 0 (high voltage range)

 * @tune1: DFLL tuning register 1

 * @assert_dvco_reset: fn ptr to place the DVCO in reset

 * @deassert_dvco_reset: fn ptr to release the DVCO reset

 * @set_clock_trimmers_high: fn ptr to tune clock trimmers for high voltage

 * @set_clock_trimmers_low: fn ptr to tune clock trimmers for low voltage

 */

struct tegra_dfll_soc_data {

	struct device *dev;

	unsigned int min_millivolts;

	u32 tune0_low;

	u32 tune0_high;

	u32 tune1;

	void (*init_clock_trimmers)(void);

	void (*set_clock_trimmers_high)(void);

	void (*set_clock_trimmers_low)(void);

};

int tegra_dfll_register(struct platform_device *pdev,

			struct tegra_dfll_soc_data *soc);

int tegra_dfll_unregister(struct platform_device *pdev);

int tegra_dfll_runtime_suspend(struct device *dev);

int tegra_dfll_runtime_resume(struct device *dev);

#endif /* __DRIVERS_CLK_TEGRA_CLK_DFLL_H */