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Commit 22a9bbe4 authored by Deepak Katragadda's avatar Deepak Katragadda Committed by Channagoud Kadabi
Browse files

ARM: dts: msm: Add the clock definitions for MSMSKUNK 



Add the clock definitions needed to support clients
on MSMSKUNK.

CRs-Fixed: 1050511
Change-Id: I34cbbc733297a85f70f4c66de655d11f53e2ad27
Signed-off-by: default avatarDeepak Katragadda <dkatraga@codeaurora.org>
parent 2686fecb

arch/arm64/boot/dts/qcom/msmskunk.dtsi

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@@ -11,6 +11,11 @@ 
 */



#include "skeleton64.dtsi"

#include <dt-bindings/clock/qcom,gcc-skunk.h>

#include <dt-bindings/clock/qcom,camcc-skunk.h>

#include <dt-bindings/clock/qcom,dispcc-skunk.h>

#include <dt-bindings/clock/qcom,gpucc-skunk.h>

#include <dt-bindings/clock/qcom,videocc-skunk.h>



/ {

	model = "Qualcomm Technologies, Inc. MSM SKUNK";

include/dt-bindings/clock/qcom,camcc-skunk.h

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/*

 * Copyright (c) 2016, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



#ifndef _DT_BINDINGS_CLK_MSM_CAM_CC_SKUNK_H

#define _DT_BINDINGS_CLK_MSM_CAM_CC_SKUNK_H



#define CAM_CC_BPS_AHB_CLK					0

#define CAM_CC_BPS_AREG_CLK					1

#define CAM_CC_BPS_AXI_CLK					2

#define CAM_CC_BPS_CLK						3

#define CAM_CC_BPS_CLK_SRC					4

#define CAM_CC_CAMNOC_ATB_CLK					5

#define CAM_CC_CAMNOC_AXI_CLK					6

#define CAM_CC_CCI_CLK						7

#define CAM_CC_CCI_CLK_SRC					8

#define CAM_CC_CPAS_AHB_CLK					9

#define CAM_CC_CPHY_RX_CLK_SRC					10

#define CAM_CC_CSI0PHYTIMER_CLK					11

#define CAM_CC_CSI0PHYTIMER_CLK_SRC				12

#define CAM_CC_CSI1PHYTIMER_CLK					13

#define CAM_CC_CSI1PHYTIMER_CLK_SRC				14

#define CAM_CC_CSI2PHYTIMER_CLK					15

#define CAM_CC_CSI2PHYTIMER_CLK_SRC				16

#define CAM_CC_CSIPHY0_CLK					17

#define CAM_CC_CSIPHY1_CLK					18

#define CAM_CC_CSIPHY2_CLK					19

#define CAM_CC_DEBUG_CLK					20

#define CAM_CC_FAST_AHB_CLK_SRC					21

#define CAM_CC_FD_CORE_CLK					22

#define CAM_CC_FD_CORE_CLK_SRC					23

#define CAM_CC_FD_CORE_UAR_CLK					24

#define CAM_CC_ICP_APB_CLK					25

#define CAM_CC_ICP_ATB_CLK					26

#define CAM_CC_ICP_CLK						27

#define CAM_CC_ICP_CLK_SRC					28

#define CAM_CC_ICP_CTI_CLK					29

#define CAM_CC_ICP_TS_CLK					30

#define CAM_CC_IFE_0_AXI_CLK					31

#define CAM_CC_IFE_0_CLK					32

#define CAM_CC_IFE_0_CLK_SRC					33

#define CAM_CC_IFE_0_CPHY_RX_CLK				34

#define CAM_CC_IFE_0_CSID_CLK					35

#define CAM_CC_IFE_0_CSID_CLK_SRC				36

#define CAM_CC_IFE_0_DSP_CLK					37

#define CAM_CC_IFE_1_AXI_CLK					38

#define CAM_CC_IFE_1_CLK					39

#define CAM_CC_IFE_1_CLK_SRC					40

#define CAM_CC_IFE_1_CPHY_RX_CLK				41

#define CAM_CC_IFE_1_CSID_CLK					42

#define CAM_CC_IFE_1_CSID_CLK_SRC				43

#define CAM_CC_IFE_1_DSP_CLK					44

#define CAM_CC_IFE_LITE_CLK					45

#define CAM_CC_IFE_LITE_CLK_SRC					46

#define CAM_CC_IFE_LITE_CPHY_RX_CLK				47

#define CAM_CC_IFE_LITE_CSID_CLK				48

#define CAM_CC_IFE_LITE_CSID_CLK_SRC				49

#define CAM_CC_IPE_0_AHB_CLK					50

#define CAM_CC_IPE_0_AREG_CLK					51

#define CAM_CC_IPE_0_AXI_CLK					52

#define CAM_CC_IPE_0_CLK					53

#define CAM_CC_IPE_0_CLK_SRC					54

#define CAM_CC_IPE_1_AHB_CLK					55

#define CAM_CC_IPE_1_AREG_CLK					56

#define CAM_CC_IPE_1_AXI_CLK					57

#define CAM_CC_IPE_1_CLK					58

#define CAM_CC_IPE_1_CLK_SRC					59

#define CAM_CC_JPEG_CLK						60

#define CAM_CC_JPEG_CLK_SRC					61

#define CAM_CC_LRME_CLK						62

#define CAM_CC_LRME_CLK_SRC					63

#define CAM_CC_MCLK0_CLK					64

#define CAM_CC_MCLK0_CLK_SRC					65

#define CAM_CC_MCLK1_CLK					66

#define CAM_CC_MCLK1_CLK_SRC					67

#define CAM_CC_MCLK2_CLK					68

#define CAM_CC_MCLK2_CLK_SRC					69

#define CAM_CC_MCLK3_CLK					70

#define CAM_CC_MCLK3_CLK_SRC					71

#define CAM_CC_PLL0						72

#define CAM_CC_PLL0_OUT_EVEN					73

#define CAM_CC_PLL0_OUT_MAIN					74

#define CAM_CC_PLL0_OUT_ODD					75

#define CAM_CC_PLL0_OUT_TEST					76

#define CAM_CC_PLL1						77

#define CAM_CC_PLL1_OUT_EVEN					78

#define CAM_CC_PLL1_OUT_MAIN					79

#define CAM_CC_PLL1_OUT_ODD					80

#define CAM_CC_PLL1_OUT_TEST					81

#define CAM_CC_PLL2						82

#define CAM_CC_PLL2_OUT_EVEN					83

#define CAM_CC_PLL2_OUT_MAIN					84

#define CAM_CC_PLL2_OUT_ODD					85

#define CAM_CC_PLL2_OUT_TEST					86

#define CAM_CC_PLL3						87

#define CAM_CC_PLL3_OUT_EVEN					88

#define CAM_CC_PLL3_OUT_MAIN					89

#define CAM_CC_PLL3_OUT_ODD					90

#define CAM_CC_PLL3_OUT_TEST					91

#define CAM_CC_PLL_TEST_CLK					92

#define CAM_CC_SLOW_AHB_CLK_SRC					93

#define CAM_CC_SOC_AHB_CLK					94

#define CAM_CC_SPDM_BPS_CLK					95

#define CAM_CC_SPDM_IFE_0_CLK					96

#define CAM_CC_SPDM_IFE_0_CSID_CLK				97

#define CAM_CC_SPDM_IPE_0_CLK					98

#define CAM_CC_SPDM_IPE_1_CLK					99

#define CAM_CC_SPDM_JPEG_CLK					100

#define CAM_CC_SYS_TMR_CLK					101



#define TITAN_CAM_CC_BPS_BCR					0

#define TITAN_CAM_CC_CAMNOC_BCR					1

#define TITAN_CAM_CC_CCI_BCR					2

#define TITAN_CAM_CC_CPAS_BCR					3

#define TITAN_CAM_CC_CSI0PHY_BCR				4

#define TITAN_CAM_CC_CSI1PHY_BCR				5

#define TITAN_CAM_CC_CSI2PHY_BCR				6

#define TITAN_CAM_CC_FD_BCR					7

#define TITAN_CAM_CC_ICP_BCR					8

#define TITAN_CAM_CC_IFE_0_BCR					9

#define TITAN_CAM_CC_IFE_1_BCR					10

#define TITAN_CAM_CC_IFE_LITE_BCR				11

#define TITAN_CAM_CC_IPE_0_BCR					12

#define TITAN_CAM_CC_IPE_1_BCR					13

#define TITAN_CAM_CC_JPEG_BCR					14

#define TITAN_CAM_CC_LRME_BCR					15

#define TITAN_CAM_CC_MCLK0_BCR					16

#define TITAN_CAM_CC_MCLK1_BCR					17

#define TITAN_CAM_CC_MCLK2_BCR					18

#define TITAN_CAM_CC_MCLK3_BCR					19

#define TITAN_CAM_CC_TITAN_TOP_BCR				20



#endif

include/dt-bindings/clock/qcom,dispcc-skunk.h

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/*

 * Copyright (c) 2016, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



#ifndef _DT_BINDINGS_CLK_MSM_DISP_CC_SKUNK_H

#define _DT_BINDINGS_CLK_MSM_DISP_CC_SKUNK_H



#define DISP_CC_DEBUG_CLK					0

#define DISP_CC_MDSS_AHB_CLK					1

#define DISP_CC_MDSS_AXI_CLK					2

#define DISP_CC_MDSS_BYTE0_CLK					3

#define DISP_CC_MDSS_BYTE0_CLK_SRC				4

#define DISP_CC_MDSS_BYTE0_INTF_CLK				5

#define DISP_CC_MDSS_BYTE1_CLK					6

#define DISP_CC_MDSS_BYTE1_CLK_SRC				7

#define DISP_CC_MDSS_BYTE1_INTF_CLK				8

#define DISP_CC_MDSS_DP_AUX_CLK					9

#define DISP_CC_MDSS_DP_AUX_CLK_SRC				10

#define DISP_CC_MDSS_DP_CRYPTO_CLK				11

#define DISP_CC_MDSS_DP_CRYPTO_CLK_SRC				12

#define DISP_CC_MDSS_DP_LINK_CLK				13

#define DISP_CC_MDSS_DP_LINK_CLK_SRC				14

#define DISP_CC_MDSS_DP_LINK_INTF_CLK				15

#define DISP_CC_MDSS_DP_PIXEL1_CLK				16

#define DISP_CC_MDSS_DP_PIXEL1_CLK_SRC				17

#define DISP_CC_MDSS_DP_PIXEL_CLK				18

#define DISP_CC_MDSS_DP_PIXEL_CLK_SRC				19

#define DISP_CC_MDSS_ESC0_CLK					20

#define DISP_CC_MDSS_ESC0_CLK_SRC				21

#define DISP_CC_MDSS_ESC1_CLK					22

#define DISP_CC_MDSS_ESC1_CLK_SRC				23

#define DISP_CC_MDSS_MDP_CLK					24

#define DISP_CC_MDSS_MDP_CLK_SRC				25

#define DISP_CC_MDSS_MDP_LUT_CLK				26

#define DISP_CC_MDSS_PCLK0_CLK					27

#define DISP_CC_MDSS_PCLK0_CLK_SRC				28

#define DISP_CC_MDSS_PCLK1_CLK					29

#define DISP_CC_MDSS_PCLK1_CLK_SRC				30

#define DISP_CC_MDSS_QDSS_AT_CLK				31

#define DISP_CC_MDSS_QDSS_TSCTR_DIV8_CLK			32

#define DISP_CC_MDSS_ROT_CLK					33

#define DISP_CC_MDSS_ROT_CLK_SRC				34

#define DISP_CC_MDSS_RSCC_AHB_CLK				35

#define DISP_CC_MDSS_RSCC_VSYNC_CLK				36

#define DISP_CC_MDSS_SPDM_DEBUG_CLK				37

#define DISP_CC_MDSS_SPDM_DP_CRYPTO_CLK				38

#define DISP_CC_MDSS_SPDM_DP_PIXEL1_CLK				39

#define DISP_CC_MDSS_SPDM_DP_PIXEL_CLK				40

#define DISP_CC_MDSS_SPDM_MDP_CLK				41

#define DISP_CC_MDSS_SPDM_PCLK0_CLK				42

#define DISP_CC_MDSS_SPDM_PCLK1_CLK				43

#define DISP_CC_MDSS_SPDM_ROT_CLK				44

#define DISP_CC_MDSS_VSYNC_CLK					45

#define DISP_CC_MDSS_VSYNC_CLK_SRC				46

#define DISP_CC_PLL0						47

#define DISP_CC_PLL0_OUT_EVEN					48

#define DISP_CC_PLL0_OUT_MAIN					49

#define DISP_CC_PLL0_OUT_ODD					50

#define DISP_CC_PLL0_OUT_TEST					51



#define DISP_CC_DISP_CC_MDSS_CORE_BCR				0

#define DISP_CC_DISP_CC_MDSS_GCC_CLOCKS_BCR			1

#define DISP_CC_DISP_CC_MDSS_RSCC_BCR				2

#define DISP_CC_DISP_CC_MDSS_SPDM_BCR				3



#endif

include/dt-bindings/clock/qcom,gcc-skunk.h

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/*

 * Copyright (c) 2016, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



#ifndef _DT_BINDINGS_CLK_MSM_GCC_SKUNK_H

#define _DT_BINDINGS_CLK_MSM_GCC_SKUNK_H



#define GCC_AGGRE_NOC_PCIE_TBU_CLK				0

#define GCC_AGGRE_UFS_CARD_AXI_CLK				1

#define GCC_AGGRE_UFS_PHY_AXI_CLK				2

#define GCC_AGGRE_USB3_PRIM_AXI_CLK				3

#define GCC_AGGRE_USB3_SEC_AXI_CLK				4

#define GCC_BOOT_ROM_AHB_CLK					5

#define GCC_CAMERA_AHB_CLK					6

#define GCC_CAMERA_AXI_CLK					7

#define GCC_CAMERA_XO_CLK					8

#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK				9

#define GCC_CFG_NOC_USB3_SEC_AXI_CLK				10

#define GCC_CPUSS_AHB_CLK					11

#define GCC_CPUSS_AHB_CLK_SRC					12

#define GCC_CPUSS_DVM_BUS_CLK					13

#define GCC_CPUSS_GNOC_CLK					14

#define GCC_CPUSS_RBCPR_CLK					15

#define GCC_CPUSS_RBCPR_CLK_SRC					16

#define GCC_CXO_TX1_CLKREF_CLK					17

#define GCC_DDRSS_GPU_AXI_CLK					18

#define GCC_DISP_AHB_CLK					19

#define GCC_DISP_AXI_CLK					20

#define GCC_DISP_XO_CLK						21

#define GCC_GP1_CLK						22

#define GCC_GP1_CLK_SRC						23

#define GCC_GP2_CLK						24

#define GCC_GP2_CLK_SRC						25

#define GCC_GP3_CLK						26

#define GCC_GP3_CLK_SRC						27

#define GCC_GPU_CFG_AHB_CLK					28

#define GCC_GPU_MEMNOC_GFX_CLK					29

#define GCC_GPU_SNOC_DVM_GFX_CLK				30

#define GCC_MMSS_QM_AHB_CLK					31

#define GCC_MMSS_QM_CORE_CLK					32

#define GCC_MMSS_QM_CORE_CLK_SRC				33

#define GCC_PCIE_0_AUX_CLK					34

#define GCC_PCIE_0_AUX_CLK_SRC					35

#define GCC_PCIE_0_CFG_AHB_CLK					36

#define GCC_PCIE_0_CLKREF_CLK					37

#define GCC_PCIE_0_MSTR_AXI_CLK					38

#define GCC_PCIE_0_PIPE_CLK					39

#define GCC_PCIE_0_SLV_AXI_CLK					40

#define GCC_PCIE_0_SLV_Q2A_AXI_CLK				41

#define GCC_PCIE_1_AUX_CLK					42

#define GCC_PCIE_1_AUX_CLK_SRC					43

#define GCC_PCIE_1_CFG_AHB_CLK					44

#define GCC_PCIE_1_CLKREF_CLK					45

#define GCC_PCIE_1_MSTR_AXI_CLK					46

#define GCC_PCIE_1_PIPE_CLK					47

#define GCC_PCIE_1_SLV_AXI_CLK					48

#define GCC_PCIE_1_SLV_Q2A_AXI_CLK				49

#define GCC_PCIE_PHY_AUX_CLK					50

#define GCC_PCIE_PHY_REFGEN_CLK					51

#define GCC_PCIE_PHY_REFGEN_CLK_SRC				52

#define GCC_PDM2_CLK						53

#define GCC_PDM2_CLK_SRC					54

#define GCC_PDM_AHB_CLK						55

#define GCC_PDM_XO4_CLK						56

#define GCC_PRNG_AHB_CLK					57

#define GCC_QMIP_CAMERA_AHB_CLK					58

#define GCC_QMIP_DISP_AHB_CLK					59

#define GCC_QMIP_VIDEO_AHB_CLK					60

#define GCC_QUPV3_WRAP0_CORE_2X_CLK				61

#define GCC_QUPV3_WRAP0_CORE_2X_CLK_SRC				62

#define GCC_QUPV3_WRAP0_CORE_CLK				63

#define GCC_QUPV3_WRAP0_S0_CLK					64

#define GCC_QUPV3_WRAP0_S0_CLK_SRC				65

#define GCC_QUPV3_WRAP0_S1_CLK					66

#define GCC_QUPV3_WRAP0_S1_CLK_SRC				67

#define GCC_QUPV3_WRAP0_S2_CLK					68

#define GCC_QUPV3_WRAP0_S2_CLK_SRC				69

#define GCC_QUPV3_WRAP0_S3_CLK					70

#define GCC_QUPV3_WRAP0_S3_CLK_SRC				71

#define GCC_QUPV3_WRAP0_S4_CLK					72

#define GCC_QUPV3_WRAP0_S4_CLK_SRC				73

#define GCC_QUPV3_WRAP0_S5_CLK					74

#define GCC_QUPV3_WRAP0_S5_CLK_SRC				75

#define GCC_QUPV3_WRAP0_S6_CLK					76

#define GCC_QUPV3_WRAP0_S6_CLK_SRC				77

#define GCC_QUPV3_WRAP0_S7_CLK					78

#define GCC_QUPV3_WRAP0_S7_CLK_SRC				79

#define GCC_QUPV3_WRAP1_CORE_2X_CLK				80

#define GCC_QUPV3_WRAP1_CORE_CLK				81

#define GCC_QUPV3_WRAP1_S0_CLK					82

#define GCC_QUPV3_WRAP1_S0_CLK_SRC				83

#define GCC_QUPV3_WRAP1_S1_CLK					84

#define GCC_QUPV3_WRAP1_S1_CLK_SRC				85

#define GCC_QUPV3_WRAP1_S2_CLK					86

#define GCC_QUPV3_WRAP1_S2_CLK_SRC				87

#define GCC_QUPV3_WRAP1_S3_CLK					88

#define GCC_QUPV3_WRAP1_S3_CLK_SRC				89

#define GCC_QUPV3_WRAP1_S4_CLK					90

#define GCC_QUPV3_WRAP1_S4_CLK_SRC				91

#define GCC_QUPV3_WRAP1_S5_CLK					92

#define GCC_QUPV3_WRAP1_S5_CLK_SRC				93

#define GCC_QUPV3_WRAP1_S6_CLK					94

#define GCC_QUPV3_WRAP1_S6_CLK_SRC				95

#define GCC_QUPV3_WRAP1_S7_CLK					96

#define GCC_QUPV3_WRAP1_S7_CLK_SRC				97

#define GCC_QUPV3_WRAP_0_M_AHB_CLK				98

#define GCC_QUPV3_WRAP_0_S_AHB_CLK				99

#define GCC_QUPV3_WRAP_1_M_AHB_CLK				100

#define GCC_QUPV3_WRAP_1_S_AHB_CLK				101

#define GCC_RX1_USB2_CLKREF_CLK					102

#define GCC_RX2_QLINK_CLKREF_CLK				103

#define GCC_RX3_MODEM_CLKREF_CLK				104

#define GCC_SDCC2_AHB_CLK					105

#define GCC_SDCC2_APPS_CLK					106

#define GCC_SDCC2_APPS_CLK_SRC					107

#define GCC_SDCC4_AHB_CLK					108

#define GCC_SDCC4_APPS_CLK					109

#define GCC_SDCC4_APPS_CLK_SRC					110

#define GCC_SYS_NOC_CPUSS_AHB_CLK				111

#define GCC_TSIF_AHB_CLK					112

#define GCC_TSIF_INACTIVITY_TIMERS_CLK				113

#define GCC_TSIF_REF_CLK					114

#define GCC_TSIF_REF_CLK_SRC					115

#define GCC_UFS_CARD_AHB_CLK					116

#define GCC_UFS_CARD_AXI_CLK					117

#define GCC_UFS_CARD_AXI_CLK_SRC				118

#define GCC_UFS_CARD_CLKREF_CLK					119

#define GCC_UFS_CARD_ICE_CORE_CLK				120

#define GCC_UFS_CARD_ICE_CORE_CLK_SRC				121

#define GCC_UFS_CARD_PHY_AUX_CLK				122

#define GCC_UFS_CARD_PHY_AUX_CLK_SRC				123

#define GCC_UFS_CARD_RX_SYMBOL_0_CLK				124

#define GCC_UFS_CARD_RX_SYMBOL_1_CLK				125

#define GCC_UFS_CARD_TX_SYMBOL_0_CLK				126

#define GCC_UFS_CARD_UNIPRO_CORE_CLK				127

#define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC			128

#define GCC_UFS_MEM_CLKREF_CLK					129

#define GCC_UFS_PHY_AHB_CLK					130

#define GCC_UFS_PHY_AXI_CLK					131

#define GCC_UFS_PHY_AXI_CLK_SRC					132

#define GCC_UFS_PHY_ICE_CORE_CLK				133

#define GCC_UFS_PHY_ICE_CORE_CLK_SRC				134

#define GCC_UFS_PHY_PHY_AUX_CLK					135

#define GCC_UFS_PHY_PHY_AUX_CLK_SRC				136

#define GCC_UFS_PHY_RX_SYMBOL_0_CLK				137

#define GCC_UFS_PHY_RX_SYMBOL_1_CLK				138

#define GCC_UFS_PHY_TX_SYMBOL_0_CLK				139

#define GCC_UFS_PHY_UNIPRO_CORE_CLK				140

#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC				141

#define GCC_USB30_PRIM_MASTER_CLK				142

#define GCC_USB30_PRIM_MASTER_CLK_SRC				143

#define GCC_USB30_PRIM_MOCK_UTMI_CLK				144

#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC			145

#define GCC_USB30_PRIM_SLEEP_CLK				146

#define GCC_USB30_SEC_MASTER_CLK				147

#define GCC_USB30_SEC_MASTER_CLK_SRC				148

#define GCC_USB30_SEC_MOCK_UTMI_CLK				149

#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC				150

#define GCC_USB30_SEC_SLEEP_CLK					151

#define GCC_USB3_PRIM_CLKREF_CLK				152

#define GCC_USB3_PRIM_PHY_AUX_CLK				153

#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC				154

#define GCC_USB3_PRIM_PHY_COM_AUX_CLK				155

#define GCC_USB3_PRIM_PHY_PIPE_CLK				156

#define GCC_USB3_SEC_CLKREF_CLK					157

#define GCC_USB3_SEC_PHY_AUX_CLK				158

#define GCC_USB3_SEC_PHY_AUX_CLK_SRC				159

#define GCC_USB3_SEC_PHY_COM_AUX_CLK				160

#define GCC_USB3_SEC_PHY_PIPE_CLK				161

#define GCC_USB_PHY_CFG_AHB2PHY_CLK				162

#define GCC_VIDEO_AHB_CLK					163

#define GCC_VIDEO_AXI_CLK					164

#define GCC_VIDEO_XO_CLK					165

#define GPLL0							166

#define GPLL0_OUT_EVEN						167

#define GPLL0_OUT_MAIN						168

#define GPLL0_OUT_ODD						169

#define GPLL0_OUT_TEST						170

#define GPLL1							171

#define GPLL1_OUT_EVEN						172

#define GPLL1_OUT_MAIN						173

#define GPLL1_OUT_ODD						174

#define GPLL1_OUT_TEST						175

#define GPLL2							176

#define GPLL2_OUT_EVEN						177

#define GPLL2_OUT_MAIN						178

#define GPLL2_OUT_ODD						179

#define GPLL2_OUT_TEST						180

#define GPLL3							181

#define GPLL3_OUT_EVEN						182

#define GPLL3_OUT_MAIN						183

#define GPLL3_OUT_ODD						184

#define GPLL3_OUT_TEST						185

#define GPLL4							186

#define GPLL4_OUT_EVEN						187

#define GPLL4_OUT_MAIN						188

#define GPLL4_OUT_ODD						189

#define GPLL4_OUT_TEST						190

#define GPLL5							191

#define GPLL5_OUT_EVEN						192

#define GPLL5_OUT_MAIN						193

#define GPLL5_OUT_ODD						194

#define GPLL5_OUT_TEST						195

#define GPLL6							196

#define GPLL6_OUT_EVEN						197

#define GPLL6_OUT_MAIN						198

#define GPLL6_OUT_ODD						199

#define GPLL6_OUT_TEST						200



#define GCC_GPU_BCR						0

#define GCC_MMSS_BCR						1

#define GCC_PCIE_0_BCR						2

#define GCC_PCIE_1_BCR						3

#define GCC_PCIE_PHY_BCR					4

#define GCC_PDM_BCR						5

#define GCC_PRNG_BCR						6

#define GCC_QUPV3_WRAPPER_0_BCR					7

#define GCC_QUPV3_WRAPPER_1_BCR					8

#define GCC_SDCC2_BCR						9

#define GCC_SDCC4_BCR						10

#define GCC_TSIF_BCR						11

#define GCC_UFS_CARD_BCR					12

#define GCC_UFS_PHY_BCR						13

#define GCC_USB30_PRIM_BCR					14

#define GCC_USB30_SEC_BCR					15

#define GCC_USB_PHY_CFG_AHB2PHY_BCR				16



#endif

include/dt-bindings/clock/qcom,gpucc-skunk.h

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/*

 * Copyright (c) 2016, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



#ifndef _DT_BINDINGS_CLK_MSM_GPU_CC_SKUNK_H

#define _DT_BINDINGS_CLK_MSM_GPU_CC_SKUNK_H



#define GPU_CC_ACD_AHB_CLK					0

#define GPU_CC_ACD_CXO_CLK					1

#define GPU_CC_AHB_CLK						2

#define GPU_CC_CRC_AHB_CLK					3

#define GPU_CC_CX_APB_CLK					4

#define GPU_CC_CX_GFX3D_CLK					5

#define GPU_CC_CX_GFX3D_SLV_CLK					6

#define GPU_CC_CX_GMU_CLK					7

#define GPU_CC_CX_QDSS_AT_CLK					8

#define GPU_CC_CX_QDSS_TRIG_CLK					9

#define GPU_CC_CX_QDSS_TSCTR_CLK				10

#define GPU_CC_CX_SNOC_DVM_CLK					11

#define GPU_CC_CXO_AON_CLK					12

#define GPU_CC_CXO_CLK						13

#define GPU_CC_DEBUG_CLK					14

#define GPU_CC_GX_CXO_CLK					15

#define GPU_CC_GX_GMU_CLK					16

#define GPU_CC_GX_QDSS_TSCTR_CLK				17

#define GPU_CC_GX_VSENSE_CLK					18

#define GPU_CC_PLL0						19

#define GPU_CC_PLL0_OUT_EVEN					20

#define GPU_CC_PLL0_OUT_MAIN					21

#define GPU_CC_PLL0_OUT_ODD					22

#define GPU_CC_PLL0_OUT_TEST					23

#define GPU_CC_PLL1						24

#define GPU_CC_PLL1_OUT_EVEN					25

#define GPU_CC_PLL1_OUT_MAIN					26

#define GPU_CC_PLL1_OUT_ODD					27

#define GPU_CC_PLL1_OUT_TEST					28

#define GPU_CC_PLL_TEST_CLK					29

#define GPU_CC_RBCPR_AHB_CLK					30

#define GPU_CC_RBCPR_CLK					31

#define GPU_CC_RBCPR_CLK_SRC					32

#define GPU_CC_SLEEP_CLK					33

#define GPU_CC_SPDM_GX_GFX3D_DIV_CLK				34



#define GPUCC_GPU_CC_ACD_BCR					0

#define GPUCC_GPU_CC_CX_BCR					1

#define GPUCC_GPU_CC_GFX3D_AON_BCR				2

#define GPUCC_GPU_CC_GMU_BCR					3

#define GPUCC_GPU_CC_GX_BCR					4

#define GPUCC_GPU_CC_RBCPR_BCR					5

#define GPUCC_GPU_CC_SPDM_BCR					6

#define GPUCC_GPU_CC_XO_BCR					7



#endif