stmmac: rename the gmac as dwmac1000 and split core and dma parts (21d437cc) · Commits · e / devices / android_kernel_fairphone_FP3

drivers/net/stmmac/Makefile

+3 −2

Original line number	Original line	Diff line number	Diff line
	obj-$(CONFIG_STMMAC_ETH) += stmmac.o		obj-$(CONFIG_STMMAC_ETH) += stmmac.o
	stmmac-$(CONFIG_STMMAC_TIMER) += stmmac_timer.o		stmmac-$(CONFIG_STMMAC_TIMER) += stmmac_timer.o
	stmmac-objs:= stmmac_main.o stmmac_ethtool.o stmmac_mdio.o dwmac_lib.o \		stmmac-objs:= stmmac_main.o stmmac_ethtool.o stmmac_mdio.o \
	dwmac100.o gmac.o $(stmmac-y)		dwmac_lib.o dwmac1000_core.o dwmac1000_dma.o \
			dwmac100.o $(stmmac-y)

drivers/net/stmmac/common.h

+1 −1

Original line number	Original line	Diff line number	Diff line
	@@ -224,7 +224,7 @@ struct mac_device_info {
	struct mac_link link;		struct mac_link link;
	};		};

	struct mac_device_info *gmac_setup(unsigned long addr);		struct mac_device_info *dwmac1000_setup(unsigned long addr);
	struct mac_device_info *dwmac100_setup(unsigned long addr);		struct mac_device_info *dwmac100_setup(unsigned long addr);

	extern void stmmac_set_mac_addr(unsigned long ioaddr, u8 addr[6],		extern void stmmac_set_mac_addr(unsigned long ioaddr, u8 addr[6],

drivers/net/stmmac/descs.h

+2 −2

Original line number	Original line	Diff line number	Diff line
	/*******************************************************************************		/*******************************************************************************
	Header File to describe the DMA descriptors		Header File to describe the DMA descriptors.
	Use enhanced descriptors in case of GMAC Cores.		Enhanced descriptors have been in case of DWMAC1000 Cores.

	This program is free software; you can redistribute it and/or modify it		This program is free software; you can redistribute it and/or modify it
	under the terms and conditions of the GNU General Public License,		under the terms and conditions of the GNU General Public License,

drivers/net/stmmac/gmac.h→drivers/net/stmmac/dwmac1000.h

+18 −1

Original line number	Original line	Diff line number	Diff line
	@@ -20,6 +20,10 @@
	Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>		Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
	*******************************************************************************/		*******************************************************************************/

			#include <linux/netdevice.h>
			#include <linux/phy.h>
			#include "common.h"

	#define GMAC_CONTROL 0x00000000 /* Configuration */		#define GMAC_CONTROL 0x00000000 /* Configuration */
	#define GMAC_FRAME_FILTER 0x00000004 /* Frame Filter */		#define GMAC_FRAME_FILTER 0x00000004 /* Frame Filter */
	#define GMAC_HASH_HIGH 0x00000008 /* Multicast Hash Table High */		#define GMAC_HASH_HIGH 0x00000008 /* Multicast Hash Table High */
	@@ -32,7 +36,7 @@
	#define GMAC_WAKEUP_FILTER 0x00000028 /* Wake-up Frame Filter */		#define GMAC_WAKEUP_FILTER 0x00000028 /* Wake-up Frame Filter */

	#define GMAC_INT_STATUS 0x00000038 /* interrupt status register */		#define GMAC_INT_STATUS 0x00000038 /* interrupt status register */
	enum gmac_irq_status {		enum dwmac1000_irq_status {
	time_stamp_irq = 0x0200,		time_stamp_irq = 0x0200,
	mmc_rx_csum_offload_irq = 0x0080,		mmc_rx_csum_offload_irq = 0x0080,
	mmc_tx_irq = 0x0040,		mmc_tx_irq = 0x0040,
	@@ -202,3 +206,16 @@ enum rtc_control {
	#define GMAC_MMC_RX_INTR 0x104		#define GMAC_MMC_RX_INTR 0x104
	#define GMAC_MMC_TX_INTR 0x108		#define GMAC_MMC_TX_INTR 0x108
	#define GMAC_MMC_RX_CSUM_OFFLOAD 0x208		#define GMAC_MMC_RX_CSUM_OFFLOAD 0x208

			#undef DWMAC1000_DEBUG
			/* #define DWMAC1000__DEBUG */
			#undef FRAME_FILTER_DEBUG
			/* #define FRAME_FILTER_DEBUG */
			#ifdef DWMAC1000__DEBUG
			#define DBG(fmt, args...) printk(fmt, ## args)
			#else
			#define DBG(fmt, args...) do { } while (0)
			#endif

			extern struct stmmac_dma_ops dwmac1000_dma_ops;
			extern struct stmmac_desc_ops dwmac1000_desc_ops;

drivers/net/stmmac/dwmac1000_core.c

0 → 100644

+245 −0

Original line number	Original line	Diff line number	Diff line
			/*******************************************************************************
			This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
			DWC Ether MAC 10/100/1000 Universal version 3.41a has been used for
			developing this code.

			This only implements the mac core functions for this chip.

			Copyright (C) 2007-2009 STMicroelectronics Ltd

			This program is free software; you can redistribute it and/or modify it
			under the terms and conditions of the GNU General Public License,
			version 2, as published by the Free Software Foundation.

			This program is distributed in the hope it will be useful, but WITHOUT
			ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
			FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
			more details.

			You should have received a copy of the GNU General Public License along with
			this program; if not, write to the Free Software Foundation, Inc.,
			51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

			The full GNU General Public License is included in this distribution in
			the file called "COPYING".

			Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
			*******************************************************************************/

			#include <linux/crc32.h>
			#include "dwmac1000.h"

			static void dwmac1000_core_init(unsigned long ioaddr)
			{
			u32 value = readl(ioaddr + GMAC_CONTROL);
			value \|= GMAC_CORE_INIT;
			writel(value, ioaddr + GMAC_CONTROL);

			/* STBus Bridge Configuration */
			/writel(0xc5608, ioaddr + 0x00007000);/

			/* Freeze MMC counters */
			writel(0x8, ioaddr + GMAC_MMC_CTRL);
			/* Mask GMAC interrupts */
			writel(0x207, ioaddr + GMAC_INT_MASK);

			#ifdef STMMAC_VLAN_TAG_USED
			/* Tag detection without filtering */
			writel(0x0, ioaddr + GMAC_VLAN_TAG);
			#endif
			return;
			}

			static void dwmac1000_dump_regs(unsigned long ioaddr)
			{
			int i;
			pr_info("\tDWMAC1000 regs (base addr = 0x%8x)\n", (unsigned int)ioaddr);

			for (i = 0; i < 55; i++) {
			int offset = i * 4;
			pr_info("\tReg No. %d (offset 0x%x): 0x%08x\n", i,
			offset, readl(ioaddr + offset));
			}
			return;
			}

			static void dwmac1000_set_umac_addr(unsigned long ioaddr, unsigned char *addr,
			unsigned int reg_n)
			{
			stmmac_set_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
			GMAC_ADDR_LOW(reg_n));
			}

			static void dwmac1000_get_umac_addr(unsigned long ioaddr, unsigned char *addr,
			unsigned int reg_n)
			{
			stmmac_get_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
			GMAC_ADDR_LOW(reg_n));
			}

			static void dwmac1000_set_filter(struct net_device *dev)
			{
			unsigned long ioaddr = dev->base_addr;
			unsigned int value = 0;

			DBG(KERN_INFO "%s: # mcasts %d, # unicast %d\n",
			__func__, dev->mc_count, dev->uc.count);

			if (dev->flags & IFF_PROMISC)
			value = GMAC_FRAME_FILTER_PR;
			else if ((dev->mc_count > HASH_TABLE_SIZE)
			\|\| (dev->flags & IFF_ALLMULTI)) {
			value = GMAC_FRAME_FILTER_PM; /* pass all multi */
			writel(0xffffffff, ioaddr + GMAC_HASH_HIGH);
			writel(0xffffffff, ioaddr + GMAC_HASH_LOW);
			} else if (dev->mc_count > 0) {
			int i;
			u32 mc_filter[2];
			struct dev_mc_list *mclist;

			/* Hash filter for multicast */
			value = GMAC_FRAME_FILTER_HMC;

			memset(mc_filter, 0, sizeof(mc_filter));
			for (i = 0, mclist = dev->mc_list;
			mclist && i < dev->mc_count; i++, mclist = mclist->next) {
			/* The upper 6 bits of the calculated CRC are used to
			index the contens of the hash table */
			int bit_nr =
			bitrev32(~crc32_le(~0, mclist->dmi_addr, 6)) >> 26;
			/* The most significant bit determines the register to
			* use (H/L) while the other 5 bits determine the bit
			* within the register. */
			mc_filter[bit_nr >> 5] \|= 1 << (bit_nr & 31);
			}
			writel(mc_filter[0], ioaddr + GMAC_HASH_LOW);
			writel(mc_filter[1], ioaddr + GMAC_HASH_HIGH);
			}

			/* Handle multiple unicast addresses (perfect filtering)*/
			if (dev->uc.count > GMAC_MAX_UNICAST_ADDRESSES)
			/* Switch to promiscuous mode is more than 16 addrs
			are required */
			value \|= GMAC_FRAME_FILTER_PR;
			else {
			int reg = 1;
			struct netdev_hw_addr *ha;

			list_for_each_entry(ha, &dev->uc.list, list) {
			dwmac1000_set_umac_addr(ioaddr, ha->addr, reg);
			reg++;
			}
			}

			#ifdef FRAME_FILTER_DEBUG
			/* Enable Receive all mode (to debug filtering_fail errors) */
			value \|= GMAC_FRAME_FILTER_RA;
			#endif
			writel(value, ioaddr + GMAC_FRAME_FILTER);

			DBG(KERN_INFO "\tFrame Filter reg: 0x%08x\n\tHash regs: "
			"HI 0x%08x, LO 0x%08x\n", readl(ioaddr + GMAC_FRAME_FILTER),
			readl(ioaddr + GMAC_HASH_HIGH), readl(ioaddr + GMAC_HASH_LOW));

			return;
			}

			static void dwmac1000_flow_ctrl(unsigned long ioaddr, unsigned int duplex,
			unsigned int fc, unsigned int pause_time)
			{
			unsigned int flow = 0;

			DBG(KERN_DEBUG "GMAC Flow-Control:\n");
			if (fc & FLOW_RX) {
			DBG(KERN_DEBUG "\tReceive Flow-Control ON\n");
			flow \|= GMAC_FLOW_CTRL_RFE;
			}
			if (fc & FLOW_TX) {
			DBG(KERN_DEBUG "\tTransmit Flow-Control ON\n");
			flow \|= GMAC_FLOW_CTRL_TFE;
			}

			if (duplex) {
			DBG(KERN_DEBUG "\tduplex mode: pause time: %d\n", pause_time);
			flow \|= (pause_time << GMAC_FLOW_CTRL_PT_SHIFT);
			}

			writel(flow, ioaddr + GMAC_FLOW_CTRL);
			return;
			}

			static void dwmac1000_pmt(unsigned long ioaddr, unsigned long mode)
			{
			unsigned int pmt = 0;

			if (mode == WAKE_MAGIC) {
			DBG(KERN_DEBUG "GMAC: WOL Magic frame\n");
			pmt \|= power_down \| magic_pkt_en;
			} else if (mode == WAKE_UCAST) {
			DBG(KERN_DEBUG "GMAC: WOL on global unicast\n");
			pmt \|= global_unicast;
			}

			writel(pmt, ioaddr + GMAC_PMT);
			return;
			}


			static void dwmac1000_irq_status(unsigned long ioaddr)
			{
			u32 intr_status = readl(ioaddr + GMAC_INT_STATUS);

			/* Not used events (e.g. MMC interrupts) are not handled. */
			if ((intr_status & mmc_tx_irq))
			DBG(KERN_DEBUG "GMAC: MMC tx interrupt: 0x%08x\n",
			readl(ioaddr + GMAC_MMC_TX_INTR));
			if (unlikely(intr_status & mmc_rx_irq))
			DBG(KERN_DEBUG "GMAC: MMC rx interrupt: 0x%08x\n",
			readl(ioaddr + GMAC_MMC_RX_INTR));
			if (unlikely(intr_status & mmc_rx_csum_offload_irq))
			DBG(KERN_DEBUG "GMAC: MMC rx csum offload: 0x%08x\n",
			readl(ioaddr + GMAC_MMC_RX_CSUM_OFFLOAD));
			if (unlikely(intr_status & pmt_irq)) {
			DBG(KERN_DEBUG "GMAC: received Magic frame\n");
			/* clear the PMT bits 5 and 6 by reading the PMT
			* status register. */
			readl(ioaddr + GMAC_PMT);
			}

			return;
			}

			struct stmmac_ops dwmac1000_ops = {
			.core_init = dwmac1000_core_init,
			.dump_regs = dwmac1000_dump_regs,
			.host_irq_status = dwmac1000_irq_status,
			.set_filter = dwmac1000_set_filter,
			.flow_ctrl = dwmac1000_flow_ctrl,
			.pmt = dwmac1000_pmt,
			.set_umac_addr = dwmac1000_set_umac_addr,
			.get_umac_addr = dwmac1000_get_umac_addr,
			};

			struct mac_device_info *dwmac1000_setup(unsigned long ioaddr)
			{
			struct mac_device_info *mac;
			u32 uid = readl(ioaddr + GMAC_VERSION);

			pr_info("\tDWMAC1000 - user ID: 0x%x, Synopsys ID: 0x%x\n",
			((uid & 0x0000ff00) >> 8), (uid & 0x000000ff));

			mac = kzalloc(sizeof(const struct mac_device_info), GFP_KERNEL);

			mac->mac = &dwmac1000_ops;
			mac->desc = &dwmac1000_desc_ops;
			mac->dma = &dwmac1000_dma_ops;

			mac->pmt = PMT_SUPPORTED;
			mac->link.port = GMAC_CONTROL_PS;
			mac->link.duplex = GMAC_CONTROL_DM;
			mac->link.speed = GMAC_CONTROL_FES;
			mac->mii.addr = GMAC_MII_ADDR;
			mac->mii.data = GMAC_MII_DATA;

			return mac;
			}