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Commit 2182d624 authored by Shashank Babu Chinta Venkata's avatar Shashank Babu Chinta Venkata Committed by Aravind Venkateswaran
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msm: clk: qcom: fix 10nm DSI PLL set rate sequence 



With the current implementation, re-enabling the PLL with
the same rate could result in the VCO not getting configured
correctly. In addition, certain PLL dividers may not be set
with the correct value. Fix this by correcting the XO clock
name to bi_tcxo and caching the pll dividers and restoring
them whenever PLL is re-enabled with the same rate.

Change-Id: If582e4bd37e78298d8f726ad84c9b729d32bec53
Signed-off-by: default avatarShashank Babu Chinta Venkata <sbchin@codeaurora.org>
parent 56c0a94b

drivers/clk/qcom/mdss/mdss-dsi-pll-10nm.c

+11 −2
Original line number Diff line number Diff line
@@ -603,6 +603,9 @@ static void vco_10nm_unprepare(struct clk_hw *hw) 
		pr_err("dsi pll resources not available\n");

		return;

	}

	pll->cached_cfg0 = MDSS_PLL_REG_R(pll->phy_base, PHY_CMN_CLK_CFG0);

	pll->cached_cfg1 = MDSS_PLL_REG_R(pll->phy_base, PHY_CMN_CLK_CFG1);

	pr_debug("cfg0=%d,cfg1=%d\n", pll->cached_cfg0, pll->cached_cfg1);



	pll->vco_cached_rate = clk_hw_get_rate(hw);

	dsi_pll_disable(vco);
@@ -637,6 +640,12 @@ static int vco_10nm_prepare(struct clk_hw *hw) 
			mdss_pll_resource_enable(pll, false);

			return rc;

		}

		pr_debug("cfg0=%d, cfg1=%d\n", pll->cached_cfg0,

			pll->cached_cfg1);

		MDSS_PLL_REG_W(pll->phy_base, PHY_CMN_CLK_CFG0,

					pll->cached_cfg0);

		MDSS_PLL_REG_W(pll->phy_base, PHY_CMN_CLK_CFG1,

					pll->cached_cfg1);

	}



	rc = dsi_pll_enable(vco);
@@ -1111,7 +1120,7 @@ static struct dsi_pll_vco_clk dsi0pll_vco_clk = { 
	.max_rate = 3500000000UL,

	.hw.init = &(struct clk_init_data){

			.name = "dsi0pll_vco_clk",

			.parent_names = (const char *[]){"xo_board"},

			.parent_names = (const char *[]){"bi_tcxo"},

			.num_parents = 1,

			.ops = &clk_ops_vco_10nm,

			.flags = CLK_GET_RATE_NOCACHE,
@@ -1124,7 +1133,7 @@ static struct dsi_pll_vco_clk dsi1pll_vco_clk = { 
	.max_rate = 3500000000UL,

	.hw.init = &(struct clk_init_data){

			.name = "dsi1pll_vco_clk",

			.parent_names = (const char *[]){"xo_board"},

			.parent_names = (const char *[]){"bi_tcxo"},

			.num_parents = 1,

			.ops = &clk_ops_vco_10nm,

			.flags = CLK_GET_RATE_NOCACHE,

drivers/clk/qcom/mdss/mdss-pll.h

+2 −0
Original line number Diff line number Diff line
@@ -94,6 +94,8 @@ struct mdss_pll_resources { 
	 * suspend/resume scenario. Cached the vco rate for such plls.

	 */

	unsigned long	vco_cached_rate;

	u32		cached_cfg0;

	u32		cached_cfg1;



	/* dsi/edp/hmdi pll interface type */

	u32		pll_interface_type;