msm: clk: qcom: fix 10nm DSI PLL set rate sequence

With the current implementation, re-enabling the PLL with
the same rate could result in the VCO not getting configured
correctly. In addition, certain PLL dividers may not be set
with the correct value. Fix this by correcting the XO clock
name to bi_tcxo and caching the pll dividers and restoring
them whenever PLL is re-enabled with the same rate.

Change-Id: If582e4bd37e78298d8f726ad84c9b729d32bec53
Signed-off-by: Shashank Babu Chinta Venkata <sbchin@codeaurora.org>