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Commit 2167ceab authored by Wan Zongshun's avatar Wan Zongshun Committed by Ingo Molnar
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x86/cpu: Add CLZERO detection 



AMD Fam17h processors introduce support for the CLZERO
instruction. It zeroes out the 64 byte cache line specified in
RAX.

Add the bit here to allow /proc/cpuinfo to list the feature.

Boris: we're adding this as a separate ->x86_capability leaf
because CPUID_80000008_EBX is going to contain more feature bits
and it will fill out with time.

Signed-off-by: default avatarWan Zongshun <Vincent.Wan@amd.com>
Signed-off-by: default avatarAravind Gopalakrishnan <aravind.gopalakrishnan@amd.com>
[ Wrap code in patch form, fix comments. ]
Signed-off-by: default avatarBorislav Petkov <bp@suse.de>
Cc: Andy Lutomirski <luto@kernel.org>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Denys Vlasenko <dvlasenk@redhat.com>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Huang Rui <ray.huang@amd.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Tony Luck <tony.luck@intel.com>
Link: http://lkml.kernel.org/r/1446207099-24948-4-git-send-email-bp@alien8.de


Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
parent 221836e9

arch/x86/include/asm/cpufeature.h

+4 −1
Original line number Diff line number Diff line
@@ -12,7 +12,7 @@ 
#include <asm/disabled-features.h>

#endif



#define NCAPINTS	13	/* N 32-bit words worth of info */

#define NCAPINTS	14	/* N 32-bit words worth of info */

#define NBUGINTS	1	/* N 32-bit bug flags */



/*
@@ -255,6 +255,9 @@ 
/* Intel-defined CPU QoS Sub-leaf, CPUID level 0x0000000F:1 (edx), word 12 */

#define X86_FEATURE_CQM_OCCUP_LLC (12*32+ 0) /* LLC occupancy monitoring if 1 */



/* AMD-defined CPU features, CPUID level 0x80000008 (ebx), word 13 */

#define X86_FEATURE_CLZERO	(13*32+0) /* CLZERO instruction */



/*

 * BUG word(s)

 */

arch/x86/kernel/cpu/common.c

+1 −0
Original line number Diff line number Diff line
@@ -670,6 +670,7 @@ void get_cpu_cap(struct cpuinfo_x86 *c) 


		c->x86_virt_bits = (eax >> 8) & 0xff;

		c->x86_phys_bits = eax & 0xff;

		c->x86_capability[13] = cpuid_ebx(0x80000008);

	}

#ifdef CONFIG_X86_32

	else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36))