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Commit 212952c2 authored by Deepak Katragadda's avatar Deepak Katragadda
Browse files

clk: qcom: Remove references for the debug clocks on SDM845 



The debug_clk clocks are only needed while measuring the controllers
clocks. The support for toggling those registers already exists in
the debug mux structures. Remove all debug clock structures so that
no client erroneously tries to manage it.

Change-Id: I0a3cebc067acbd9ce57f9df23c7591218add90f8
Signed-off-by: default avatarDeepak Katragadda <dkatraga@codeaurora.org>
parent dbf26f91

drivers/clk/qcom/camcc-sdm845.c

+0 −14
Original line number Diff line number Diff line
@@ -1115,19 +1115,6 @@ static struct clk_branch cam_cc_csiphy2_clk = { 
	},

};



static struct clk_branch cam_cc_debug_clk = {

	.halt_reg = 0xc008,

	.halt_check = BRANCH_HALT,

	.clkr = {

		.enable_reg = 0xc008,

		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "cam_cc_debug_clk",

			.ops = &clk_branch2_ops,

		},

	},

};



static struct clk_branch cam_cc_fd_core_clk = {

	.halt_reg = 0xb0c8,

	.halt_check = BRANCH_HALT,
@@ -1764,7 +1751,6 @@ static struct clk_regmap *cam_cc_sdm845_clocks[] = { 
	[CAM_CC_CSIPHY0_CLK] = &cam_cc_csiphy0_clk.clkr,

	[CAM_CC_CSIPHY1_CLK] = &cam_cc_csiphy1_clk.clkr,

	[CAM_CC_CSIPHY2_CLK] = &cam_cc_csiphy2_clk.clkr,

	[CAM_CC_DEBUG_CLK] = &cam_cc_debug_clk.clkr,

	[CAM_CC_FAST_AHB_CLK_SRC] = &cam_cc_fast_ahb_clk_src.clkr,

	[CAM_CC_FD_CORE_CLK] = &cam_cc_fd_core_clk.clkr,

	[CAM_CC_FD_CORE_CLK_SRC] = &cam_cc_fd_core_clk_src.clkr,

drivers/clk/qcom/dispcc-sdm845.c

+0 −14
Original line number Diff line number Diff line
@@ -478,19 +478,6 @@ static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = { 
	},

};



static struct clk_branch disp_cc_debug_clk = {

	.halt_reg = 0x600c,

	.halt_check = BRANCH_HALT,

	.clkr = {

		.enable_reg = 0x600c,

		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "disp_cc_debug_clk",

			.ops = &clk_branch2_ops,

		},

	},

};



static struct clk_branch disp_cc_mdss_ahb_clk = {

	.halt_reg = 0x4004,

	.halt_check = BRANCH_HALT,
@@ -949,7 +936,6 @@ static struct clk_branch disp_cc_mdss_vsync_clk = { 
};



static struct clk_regmap *disp_cc_sdm845_clocks[] = {

	[DISP_CC_DEBUG_CLK] = &disp_cc_debug_clk.clkr,

	[DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr,

	[DISP_CC_MDSS_AXI_CLK] = &disp_cc_mdss_axi_clk.clkr,

	[DISP_CC_MDSS_BYTE0_CLK] = &disp_cc_mdss_byte0_clk.clkr,

drivers/clk/qcom/gpucc-sdm845.c

+0 −14
Original line number Diff line number Diff line
@@ -413,19 +413,6 @@ static struct clk_branch gpu_cc_cxo_clk = { 
	},

};



static struct clk_branch gpu_cc_debug_clk = {

	.halt_reg = 0x1100,

	.halt_check = BRANCH_HALT,

	.clkr = {

		.enable_reg = 0x1100,

		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gpu_cc_debug_clk",

			.ops = &clk_branch2_ops,

		},

	},

};



static struct clk_branch gpu_cc_gx_cxo_clk = {

	.halt_reg = 0x1060,

	.halt_check = BRANCH_HALT,
@@ -544,7 +531,6 @@ static struct clk_regmap *gpu_cc_sdm845_clocks[] = { 
	[GPU_CC_CX_SNOC_DVM_CLK] = &gpu_cc_cx_snoc_dvm_clk.clkr,

	[GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr,

	[GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr,

	[GPU_CC_DEBUG_CLK] = &gpu_cc_debug_clk.clkr,

	[GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr,

	[GPU_CC_GX_CXO_CLK] = &gpu_cc_gx_cxo_clk.clkr,

	[GPU_CC_GX_GMU_CLK] = &gpu_cc_gx_gmu_clk.clkr,

drivers/clk/qcom/videocc-sdm845.c

+0 −14
Original line number Diff line number Diff line
@@ -151,19 +151,6 @@ static struct clk_branch video_cc_at_clk = { 
	},

};



static struct clk_branch video_cc_debug_clk = {

	.halt_reg = 0xa58,

	.halt_check = BRANCH_HALT,

	.clkr = {

		.enable_reg = 0xa58,

		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "video_cc_debug_clk",

			.ops = &clk_branch2_ops,

		},

	},

};



static struct clk_branch video_cc_qdss_trig_clk = {

	.halt_reg = 0x970,

	.halt_check = BRANCH_HALT,
@@ -299,7 +286,6 @@ static struct clk_branch video_cc_venus_ctl_core_clk = { 
static struct clk_regmap *video_cc_sdm845_clocks[] = {

	[VIDEO_CC_APB_CLK] = &video_cc_apb_clk.clkr,

	[VIDEO_CC_AT_CLK] = &video_cc_at_clk.clkr,

	[VIDEO_CC_DEBUG_CLK] = &video_cc_debug_clk.clkr,

	[VIDEO_CC_QDSS_TRIG_CLK] = &video_cc_qdss_trig_clk.clkr,

	[VIDEO_CC_QDSS_TSCTR_DIV8_CLK] = &video_cc_qdss_tsctr_div8_clk.clkr,

	[VIDEO_CC_VCODEC0_AXI_CLK] = &video_cc_vcodec0_axi_clk.clkr,

include/dt-bindings/clock/qcom,camcc-sdm845.h

+64 −65
Original line number Diff line number Diff line
@@ -34,71 +34,70 @@ 
#define CAM_CC_CSIPHY0_CLK					17

#define CAM_CC_CSIPHY1_CLK					18

#define CAM_CC_CSIPHY2_CLK					19

#define CAM_CC_DEBUG_CLK					20

#define CAM_CC_FAST_AHB_CLK_SRC					21

#define CAM_CC_FD_CORE_CLK					22

#define CAM_CC_FD_CORE_CLK_SRC					23

#define CAM_CC_FD_CORE_UAR_CLK					24

#define CAM_CC_ICP_APB_CLK					25

#define CAM_CC_ICP_ATB_CLK					26

#define CAM_CC_ICP_CLK						27

#define CAM_CC_ICP_CLK_SRC					28

#define CAM_CC_ICP_CTI_CLK					29

#define CAM_CC_ICP_TS_CLK					30

#define CAM_CC_IFE_0_AXI_CLK					31

#define CAM_CC_IFE_0_CLK					32

#define CAM_CC_IFE_0_CLK_SRC					33

#define CAM_CC_IFE_0_CPHY_RX_CLK				34

#define CAM_CC_IFE_0_CSID_CLK					35

#define CAM_CC_IFE_0_CSID_CLK_SRC				36

#define CAM_CC_IFE_0_DSP_CLK					37

#define CAM_CC_IFE_1_AXI_CLK					38

#define CAM_CC_IFE_1_CLK					39

#define CAM_CC_IFE_1_CLK_SRC					40

#define CAM_CC_IFE_1_CPHY_RX_CLK				41

#define CAM_CC_IFE_1_CSID_CLK					42

#define CAM_CC_IFE_1_CSID_CLK_SRC				43

#define CAM_CC_IFE_1_DSP_CLK					44

#define CAM_CC_IFE_LITE_CLK					45

#define CAM_CC_IFE_LITE_CLK_SRC					46

#define CAM_CC_IFE_LITE_CPHY_RX_CLK				47

#define CAM_CC_IFE_LITE_CSID_CLK				48

#define CAM_CC_IFE_LITE_CSID_CLK_SRC				49

#define CAM_CC_IPE_0_AHB_CLK					50

#define CAM_CC_IPE_0_AREG_CLK					51

#define CAM_CC_IPE_0_AXI_CLK					52

#define CAM_CC_IPE_0_CLK					53

#define CAM_CC_IPE_0_CLK_SRC					54

#define CAM_CC_IPE_1_AHB_CLK					55

#define CAM_CC_IPE_1_AREG_CLK					56

#define CAM_CC_IPE_1_AXI_CLK					57

#define CAM_CC_IPE_1_CLK					58

#define CAM_CC_IPE_1_CLK_SRC					59

#define CAM_CC_JPEG_CLK						60

#define CAM_CC_JPEG_CLK_SRC					61

#define CAM_CC_LRME_CLK						62

#define CAM_CC_LRME_CLK_SRC					63

#define CAM_CC_MCLK0_CLK					64

#define CAM_CC_MCLK0_CLK_SRC					65

#define CAM_CC_MCLK1_CLK					66

#define CAM_CC_MCLK1_CLK_SRC					67

#define CAM_CC_MCLK2_CLK					68

#define CAM_CC_MCLK2_CLK_SRC					69

#define CAM_CC_MCLK3_CLK					70

#define CAM_CC_MCLK3_CLK_SRC					71

#define CAM_CC_PLL0						72

#define CAM_CC_PLL0_OUT_EVEN					73

#define CAM_CC_PLL1						74

#define CAM_CC_PLL1_OUT_EVEN					75

#define CAM_CC_PLL2						76

#define CAM_CC_PLL2_OUT_EVEN					77

#define CAM_CC_PLL2_OUT_ODD					78

#define CAM_CC_PLL3						79

#define CAM_CC_PLL3_OUT_EVEN					80

#define CAM_CC_PLL_TEST_CLK					81

#define CAM_CC_SLOW_AHB_CLK_SRC					82

#define CAM_CC_SOC_AHB_CLK					83

#define CAM_CC_SYS_TMR_CLK					84

#define CAM_CC_FAST_AHB_CLK_SRC					20

#define CAM_CC_FD_CORE_CLK					21

#define CAM_CC_FD_CORE_CLK_SRC					22

#define CAM_CC_FD_CORE_UAR_CLK					23

#define CAM_CC_ICP_APB_CLK					24

#define CAM_CC_ICP_ATB_CLK					25

#define CAM_CC_ICP_CLK						26

#define CAM_CC_ICP_CLK_SRC					27

#define CAM_CC_ICP_CTI_CLK					28

#define CAM_CC_ICP_TS_CLK					29

#define CAM_CC_IFE_0_AXI_CLK					30

#define CAM_CC_IFE_0_CLK					31

#define CAM_CC_IFE_0_CLK_SRC					32

#define CAM_CC_IFE_0_CPHY_RX_CLK				33

#define CAM_CC_IFE_0_CSID_CLK					34

#define CAM_CC_IFE_0_CSID_CLK_SRC				35

#define CAM_CC_IFE_0_DSP_CLK					36

#define CAM_CC_IFE_1_AXI_CLK					37

#define CAM_CC_IFE_1_CLK					38

#define CAM_CC_IFE_1_CLK_SRC					39

#define CAM_CC_IFE_1_CPHY_RX_CLK				40

#define CAM_CC_IFE_1_CSID_CLK					41

#define CAM_CC_IFE_1_CSID_CLK_SRC				42

#define CAM_CC_IFE_1_DSP_CLK					43

#define CAM_CC_IFE_LITE_CLK					44

#define CAM_CC_IFE_LITE_CLK_SRC					45

#define CAM_CC_IFE_LITE_CPHY_RX_CLK				46

#define CAM_CC_IFE_LITE_CSID_CLK				47

#define CAM_CC_IFE_LITE_CSID_CLK_SRC				48

#define CAM_CC_IPE_0_AHB_CLK					49

#define CAM_CC_IPE_0_AREG_CLK					50

#define CAM_CC_IPE_0_AXI_CLK					51

#define CAM_CC_IPE_0_CLK					52

#define CAM_CC_IPE_0_CLK_SRC					53

#define CAM_CC_IPE_1_AHB_CLK					54

#define CAM_CC_IPE_1_AREG_CLK					55

#define CAM_CC_IPE_1_AXI_CLK					56

#define CAM_CC_IPE_1_CLK					57

#define CAM_CC_IPE_1_CLK_SRC					58

#define CAM_CC_JPEG_CLK						59

#define CAM_CC_JPEG_CLK_SRC					60

#define CAM_CC_LRME_CLK						61

#define CAM_CC_LRME_CLK_SRC					62

#define CAM_CC_MCLK0_CLK					63

#define CAM_CC_MCLK0_CLK_SRC					64

#define CAM_CC_MCLK1_CLK					65

#define CAM_CC_MCLK1_CLK_SRC					66

#define CAM_CC_MCLK2_CLK					67

#define CAM_CC_MCLK2_CLK_SRC					68

#define CAM_CC_MCLK3_CLK					69

#define CAM_CC_MCLK3_CLK_SRC					70

#define CAM_CC_PLL0						71

#define CAM_CC_PLL0_OUT_EVEN					72

#define CAM_CC_PLL1						73

#define CAM_CC_PLL1_OUT_EVEN					74

#define CAM_CC_PLL2						75

#define CAM_CC_PLL2_OUT_EVEN					76

#define CAM_CC_PLL2_OUT_ODD					77

#define CAM_CC_PLL3						78

#define CAM_CC_PLL3_OUT_EVEN					79

#define CAM_CC_PLL_TEST_CLK					80

#define CAM_CC_SLOW_AHB_CLK_SRC					81

#define CAM_CC_SOC_AHB_CLK					82

#define CAM_CC_SYS_TMR_CLK					83



#define TITAN_CAM_CC_BPS_BCR					0

#define TITAN_CAM_CC_CAMNOC_BCR					1