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Commit 20ef9e08 authored by Boojin Kim's avatar Boojin Kim Committed by Kukjin Kim
Browse files

ARM: EXYNOS: Support DMA for EXYNOS5250 SoC 



mach-exynos/dma.c is updated to support both exynos4 and exynos5.

Signed-off-by: default avatarBoojin Kim <boojin.kim@samsung.com>
Signed-off-by: default avatarKukjin Kim <kgene.kim@samsung.com>
parent 06050e55

arch/arm/mach-exynos/Kconfig

+4 −3
Original line number Diff line number Diff line
@@ -61,6 +61,7 @@ config SOC_EXYNOS5250 
	bool "SAMSUNG EXYNOS5250"

	default y

	depends on ARCH_EXYNOS5

	select SAMSUNG_DMADEV

	help

	  Enable EXYNOS5250 SoC support
@@ -70,7 +71,7 @@ config EXYNOS4_MCT 
	help

	  Use MCT (Multi Core Timer) as kernel timers



config EXYNOS4_DEV_DMA

config EXYNOS_DEV_DMA

	bool

	help

	  Compile in amba device definitions for DMA controller
@@ -228,7 +229,7 @@ config MACH_ARMLEX4210 
	select S3C_DEV_HSMMC2

	select S3C_DEV_HSMMC3

	select EXYNOS4_DEV_AHCI

	select EXYNOS4_DEV_DMA

	select EXYNOS_DEV_DMA

	select EXYNOS4_SETUP_SDHCI

	help

	  Machine support for Samsung ARMLEX4210 based on EXYNOS4210
@@ -352,7 +353,7 @@ config MACH_SMDK4212 
	select SAMSUNG_DEV_KEYPAD

	select SAMSUNG_DEV_PWM

	select EXYNOS_DEV_SYSMMU

	select EXYNOS4_DEV_DMA

	select EXYNOS_DEV_DMA

	select EXYNOS4_SETUP_I2C1

	select EXYNOS4_SETUP_I2C3

	select EXYNOS4_SETUP_I2C7

arch/arm/mach-exynos/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -51,7 +51,7 @@ obj-y += dev-uart.o 
obj-$(CONFIG_ARCH_EXYNOS4)		+= dev-audio.o

obj-$(CONFIG_EXYNOS4_DEV_AHCI)		+= dev-ahci.o

obj-$(CONFIG_EXYNOS4_DEV_DWMCI)		+= dev-dwmci.o

obj-$(CONFIG_EXYNOS4_DEV_DMA)		+= dma.o

obj-$(CONFIG_EXYNOS_DEV_DMA)		+= dma.o

obj-$(CONFIG_EXYNOS4_DEV_USB_OHCI)	+= dev-ohci.o

obj-$(CONFIG_EXYNOS_DEV_DRM)		+= dev-drm.o

obj-$(CONFIG_EXYNOS_DEV_SYSMMU)		+= dev-sysmmu.o

arch/arm/mach-exynos/dma.c

+114 −27
Original line number Diff line number Diff line
@@ -103,10 +103,45 @@ static u8 exynos4212_pdma0_peri[] = { 
	DMACH_MIPI_HSI5,

};



struct dma_pl330_platdata exynos4_pdma0_pdata;

static u8 exynos5250_pdma0_peri[] = {

	DMACH_PCM0_RX,

	DMACH_PCM0_TX,

	DMACH_PCM2_RX,

	DMACH_PCM2_TX,

	DMACH_SPI0_RX,

	DMACH_SPI0_TX,

	DMACH_SPI2_RX,

	DMACH_SPI2_TX,

	DMACH_I2S0S_TX,

	DMACH_I2S0_RX,

	DMACH_I2S0_TX,

	DMACH_I2S2_RX,

	DMACH_I2S2_TX,

	DMACH_UART0_RX,

	DMACH_UART0_TX,

	DMACH_UART2_RX,

	DMACH_UART2_TX,

	DMACH_UART4_RX,

	DMACH_UART4_TX,

	DMACH_SLIMBUS0_RX,

	DMACH_SLIMBUS0_TX,

	DMACH_SLIMBUS2_RX,

	DMACH_SLIMBUS2_TX,

	DMACH_SLIMBUS4_RX,

	DMACH_SLIMBUS4_TX,

	DMACH_AC97_MICIN,

	DMACH_AC97_PCMIN,

	DMACH_AC97_PCMOUT,

	DMACH_MIPI_HSI0,

	DMACH_MIPI_HSI2,

	DMACH_MIPI_HSI4,

	DMACH_MIPI_HSI6,

};



static struct dma_pl330_platdata exynos_pdma0_pdata;



static AMBA_AHB_DEVICE(exynos4_pdma0, "dma-pl330.0", 0x00041330,

	EXYNOS4_PA_PDMA0, {EXYNOS4_IRQ_PDMA0}, &exynos4_pdma0_pdata);

static AMBA_AHB_DEVICE(exynos_pdma0, "dma-pl330.0", 0x00041330,

	EXYNOS4_PA_PDMA0, {EXYNOS4_IRQ_PDMA0}, &exynos_pdma0_pdata);



static u8 exynos4210_pdma1_peri[] = {

	DMACH_PCM0_RX,
@@ -169,10 +204,45 @@ static u8 exynos4212_pdma1_peri[] = { 
	DMACH_MIPI_HSI7,

};



static struct dma_pl330_platdata exynos4_pdma1_pdata;

static u8 exynos5250_pdma1_peri[] = {

	DMACH_PCM0_RX,

	DMACH_PCM0_TX,

	DMACH_PCM1_RX,

	DMACH_PCM1_TX,

	DMACH_SPI1_RX,

	DMACH_SPI1_TX,

	DMACH_PWM,

	DMACH_SPDIF,

	DMACH_I2S0S_TX,

	DMACH_I2S0_RX,

	DMACH_I2S0_TX,

	DMACH_I2S1_RX,

	DMACH_I2S1_TX,

	DMACH_UART0_RX,

	DMACH_UART0_TX,

	DMACH_UART1_RX,

	DMACH_UART1_TX,

	DMACH_UART3_RX,

	DMACH_UART3_TX,

	DMACH_SLIMBUS1_RX,

	DMACH_SLIMBUS1_TX,

	DMACH_SLIMBUS3_RX,

	DMACH_SLIMBUS3_TX,

	DMACH_SLIMBUS5_RX,

	DMACH_SLIMBUS5_TX,

	DMACH_SLIMBUS0AUX_RX,

	DMACH_SLIMBUS0AUX_TX,

	DMACH_DISP1,

	DMACH_MIPI_HSI1,

	DMACH_MIPI_HSI3,

	DMACH_MIPI_HSI5,

	DMACH_MIPI_HSI7,

};



static AMBA_AHB_DEVICE(exynos4_pdma1,  "dma-pl330.1", 0x00041330,

	EXYNOS4_PA_PDMA1, {EXYNOS4_IRQ_PDMA1}, &exynos4_pdma1_pdata);

static struct dma_pl330_platdata exynos_pdma1_pdata;



static AMBA_AHB_DEVICE(exynos_pdma1,  "dma-pl330.1", 0x00041330,

	EXYNOS4_PA_PDMA1, {EXYNOS4_IRQ_PDMA1}, &exynos_pdma1_pdata);



static u8 mdma_peri[] = {

	DMACH_MTOM_0,
@@ -185,46 +255,63 @@ static u8 mdma_peri[] = { 
	DMACH_MTOM_7,

};



static struct dma_pl330_platdata exynos4_mdma1_pdata = {

static struct dma_pl330_platdata exynos_mdma1_pdata = {

	.nr_valid_peri = ARRAY_SIZE(mdma_peri),

	.peri_id = mdma_peri,

};



static AMBA_AHB_DEVICE(exynos4_mdma1,  "dma-pl330.2", 0x00041330,

	EXYNOS4_PA_MDMA1, {EXYNOS4_IRQ_MDMA1}, &exynos4_mdma1_pdata);

static AMBA_AHB_DEVICE(exynos_mdma1,  "dma-pl330.2", 0x00041330,

	EXYNOS4_PA_MDMA1, {EXYNOS4_IRQ_MDMA1}, &exynos_mdma1_pdata);



static int __init exynos4_dma_init(void)

static int __init exynos_dma_init(void)

{

	if (of_have_populated_dt())

		return 0;



	if (soc_is_exynos4210()) {

		exynos4_pdma0_pdata.nr_valid_peri =

		exynos_pdma0_pdata.nr_valid_peri =

			ARRAY_SIZE(exynos4210_pdma0_peri);

		exynos4_pdma0_pdata.peri_id = exynos4210_pdma0_peri;

		exynos4_pdma1_pdata.nr_valid_peri =

		exynos_pdma0_pdata.peri_id = exynos4210_pdma0_peri;

		exynos_pdma1_pdata.nr_valid_peri =

			ARRAY_SIZE(exynos4210_pdma1_peri);

		exynos4_pdma1_pdata.peri_id = exynos4210_pdma1_peri;

		exynos_pdma1_pdata.peri_id = exynos4210_pdma1_peri;

	} else if (soc_is_exynos4212() || soc_is_exynos4412()) {

		exynos4_pdma0_pdata.nr_valid_peri =

		exynos_pdma0_pdata.nr_valid_peri =

			ARRAY_SIZE(exynos4212_pdma0_peri);

		exynos4_pdma0_pdata.peri_id = exynos4212_pdma0_peri;

		exynos4_pdma1_pdata.nr_valid_peri =

		exynos_pdma0_pdata.peri_id = exynos4212_pdma0_peri;

		exynos_pdma1_pdata.nr_valid_peri =

			ARRAY_SIZE(exynos4212_pdma1_peri);

		exynos4_pdma1_pdata.peri_id = exynos4212_pdma1_peri;

		exynos_pdma1_pdata.peri_id = exynos4212_pdma1_peri;

	} else if (soc_is_exynos5250()) {

		exynos_pdma0_pdata.nr_valid_peri =

			ARRAY_SIZE(exynos5250_pdma0_peri);

		exynos_pdma0_pdata.peri_id = exynos5250_pdma0_peri;

		exynos_pdma1_pdata.nr_valid_peri =

			ARRAY_SIZE(exynos5250_pdma1_peri);

		exynos_pdma1_pdata.peri_id = exynos5250_pdma1_peri;



		exynos_pdma0_device.res.start = EXYNOS5_PA_PDMA0;

		exynos_pdma0_device.res.end = EXYNOS5_PA_PDMA0 + SZ_4K;

		exynos_pdma0_device.irq[0] = EXYNOS5_IRQ_PDMA0;

		exynos_pdma1_device.res.start = EXYNOS5_PA_PDMA1;

		exynos_pdma1_device.res.end = EXYNOS5_PA_PDMA1 + SZ_4K;

		exynos_pdma0_device.irq[0] = EXYNOS5_IRQ_PDMA1;

		exynos_mdma1_device.res.start = EXYNOS5_PA_MDMA1;

		exynos_mdma1_device.res.end = EXYNOS5_PA_MDMA1 + SZ_4K;

		exynos_pdma0_device.irq[0] = EXYNOS5_IRQ_MDMA1;

	}



	dma_cap_set(DMA_SLAVE, exynos4_pdma0_pdata.cap_mask);

	dma_cap_set(DMA_CYCLIC, exynos4_pdma0_pdata.cap_mask);

	amba_device_register(&exynos4_pdma0_device, &iomem_resource);

	dma_cap_set(DMA_SLAVE, exynos_pdma0_pdata.cap_mask);

	dma_cap_set(DMA_CYCLIC, exynos_pdma0_pdata.cap_mask);

	amba_device_register(&exynos_pdma0_device, &iomem_resource);



	dma_cap_set(DMA_SLAVE, exynos4_pdma1_pdata.cap_mask);

	dma_cap_set(DMA_CYCLIC, exynos4_pdma1_pdata.cap_mask);

	amba_device_register(&exynos4_pdma1_device, &iomem_resource);

	dma_cap_set(DMA_SLAVE, exynos_pdma1_pdata.cap_mask);

	dma_cap_set(DMA_CYCLIC, exynos_pdma1_pdata.cap_mask);

	amba_device_register(&exynos_pdma1_device, &iomem_resource);



	dma_cap_set(DMA_MEMCPY, exynos4_mdma1_pdata.cap_mask);

	amba_device_register(&exynos4_mdma1_device, &iomem_resource);

	dma_cap_set(DMA_MEMCPY, exynos_mdma1_pdata.cap_mask);

	amba_device_register(&exynos_mdma1_device, &iomem_resource);



	return 0;

}

arch_initcall(exynos4_dma_init);
 
arch_initcall(exynos_dma_init);

arch/arm/plat-samsung/Kconfig

+1 −1
Original line number Diff line number Diff line
@@ -291,7 +291,7 @@ config S3C_DMA 
config SAMSUNG_DMADEV

	bool

	select DMADEVICES

	select PL330_DMA if (CPU_EXYNOS4210 || CPU_S5PV210 || CPU_S5PC100 || \

	select PL330_DMA if (ARCH_EXYNOS5 || ARCH_EXYNOS4 || CPU_S5PV210 || CPU_S5PC100 || \

					CPU_S5P6450 || CPU_S5P6440)

	select ARM_AMBA

	help

arch/arm/plat-samsung/include/plat/dma-pl330.h

+1 −0
Original line number Diff line number Diff line
@@ -90,6 +90,7 @@ enum dma_ch { 
	DMACH_MIPI_HSI5,

	DMACH_MIPI_HSI6,

	DMACH_MIPI_HSI7,

	DMACH_DISP1,

	DMACH_MTOM_0,

	DMACH_MTOM_1,

	DMACH_MTOM_2,