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Commit 20b1df9f authored by Jonathan Wicks's avatar Jonathan Wicks
Browse files

msm: kgsl: Disable microcode save/restore of perf counter values on A6x 



Setting this ordinal in the microcode prevents the GPU from saving
and restoring the performance counter values across preemption. This
allows the counters to also be used for global measurements since
the values are strictly increasing.

Change-Id: I169a85d93f5d03b09365d76f2fdea54d3ff0fb6c
Signed-off-by: default avatarJonathan Wicks <jwicks@codeaurora.org>
parent 5f300da0

drivers/gpu/msm/adreno_a6xx.c

+13 −1
Original line number Diff line number Diff line
@@ -544,11 +544,20 @@ static int a6xx_microcode_load(struct adreno_device *adreno_dev) 
/* Ucode workaround masks */

#define CP_INIT_UCODE_WORKAROUND_MASK BIT(5)



/*

 * Operation mode mask

 *

 * This ordinal provides the option to disable the

 * save/restore of performance counters across preemption.

 */

#define CP_INIT_OPERATION_MODE_MASK BIT(6)



#define CP_INIT_MASK (CP_INIT_MAX_CONTEXT | \

		CP_INIT_ERROR_DETECTION_CONTROL | \

		CP_INIT_HEADER_DUMP | \

		CP_INIT_DEFAULT_RESET_STATE | \

		CP_INIT_UCODE_WORKAROUND_MASK)

		CP_INIT_UCODE_WORKAROUND_MASK | \

		CP_INIT_OPERATION_MODE_MASK)



static void _set_ordinals(struct adreno_device *adreno_dev,

		unsigned int *cmds, unsigned int count)
@@ -581,6 +590,9 @@ static void _set_ordinals(struct adreno_device *adreno_dev, 
	if (CP_INIT_MASK & CP_INIT_UCODE_WORKAROUND_MASK)

		*cmds++ = 0x00000000;



	if (CP_INIT_MASK & CP_INIT_OPERATION_MODE_MASK)

		*cmds++ = 0x00000002;



	/* Pad rest of the cmds with 0's */

	while ((unsigned int)(cmds - start) < count)

		*cmds++ = 0x0;