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Commit 20a21dbc authored by Padmanabhan Komanduru's avatar Padmanabhan Komanduru
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drm/msm/dp: update parsing of AUX configuration settings 



Extend the parsing logic for AUX settings by adding multiple settings
per configuration and parsing the register offsets. This enables the
extension to support different targets, and combinations of AUX
controller settings depending on the use case.

Change-Id: I4e6b623a4d9fafcfcc89477dfa57880eb798c350
Signed-off-by: default avatarPadmanabhan Komanduru <pkomandu@codeaurora.org>
parent eb5b60ca

Documentation/devicetree/bindings/drm/msm/sde-dp.txt

+50 −2
Original line number Diff line number Diff line
@@ -25,7 +25,46 @@ DP Controller: Required properties: 
- qcom,aux-en-gpio:			Specifies the aux-channel enable gpio.

- qcom,aux-sel-gpio:		Specifies the aux-channel select gpio.

- qcom,usbplug-cc-gpio:		Specifies the usbplug orientation gpio.

- qcom,aux-cfg-settings:	An array that specifies the DP AUX configuration settings.

- qcom,aux-cfg0-settings:		Specifies the DP AUX configuration 0 settings. The first

					entry in this array corresponds to the register offset

					within DP AUX, while the remaining entries indicate the

					programmable values.

- qcom,aux-cfg1-settings:		Specifies the DP AUX configuration 1 settings. The first

					entry in this array corresponds to the register offset

					within DP AUX, while the remaining entries indicate the

					programmable values.

- qcom,aux-cfg2-settings:		Specifies the DP AUX configuration 2 settings. The first

					entry in this array corresponds to the register offset

					within DP AUX, while the remaining entries indicate the

					programmable values.

- qcom,aux-cfg3-settings:		Specifies the DP AUX configuration 3 settings. The first

					entry in this array corresponds to the register offset

					within DP AUX, while the remaining entries indicate the

					programmable values.

- qcom,aux-cfg4-settings:		Specifies the DP AUX configuration 4 settings. The first

					entry in this array corresponds to the register offset

					within DP AUX, while the remaining entries indicate the

					programmable values.

- qcom,aux-cfg5-settings:		Specifies the DP AUX configuration 5 settings. The first

					entry in this array corresponds to the register offset

					within DP AUX, while the remaining entries indicate the

					programmable values.

- qcom,aux-cfg6-settings:		Specifies the DP AUX configuration 6 settings. The first

					entry in this array corresponds to the register offset

					within DP AUX, while the remaining entries indicate the

					programmable values.

- qcom,aux-cfg7-settings:		Specifies the DP AUX configuration 7 settings. The first

					entry in this array corresponds to the register offset

					within DP AUX, while the remaining entries indicate the

					programmable values.

- qcom,aux-cfg8-settings:		Specifies the DP AUX configuration 8 settings. The first

					entry in this array corresponds to the register offset

					within DP AUX, while the remaining entries indicate the

					programmable values.

- qcom,aux-cfg9-settings:		Specifies the DP AUX configuration 9 settings. The first

					entry in this array corresponds to the register offset

					within DP AUX, while the remaining entries indicate the

					programmable values.

- qcom,max-pclk-frequency-khz:	An integer specifying the max. pixel clock in KHz supported by Display Port.

- qcom,dp-usbpd-detection:	Phandle for the PMI regulator node for USB PHY PD detection.

- qcom,<type>-supply-entries:		A node that lists the elements of the supply used by the a particular "type" of DSI module. The module "types"
@@ -93,7 +132,16 @@ Example: 


		qcom,dp-usbpd-detection = <&pmi8998_pdphy>;



		qcom,aux-cfg-settings = [00 13 04 00 0a 26 0a 03 bb 03];

		qcom,aux-cfg0-settings = [1c 00];

		qcom,aux-cfg1-settings = [20 13 23 1d];

		qcom,aux-cfg2-settings = [24 00];

		qcom,aux-cfg3-settings = [28 00];

		qcom,aux-cfg4-settings = [2c 0a];

		qcom,aux-cfg5-settings = [30 26];

		qcom,aux-cfg6-settings = [34 0a];

		qcom,aux-cfg7-settings = [38 03];

		qcom,aux-cfg8-settings = [3c bb];

		qcom,aux-cfg9-settings = [40 03];

		qcom,max-pclk-frequency-khz = <593470>;

		pinctrl-names = "mdss_dp_active", "mdss_dp_sleep";

		pinctrl-0 = <&sde_dp_aux_active &sde_dp_usbplug_cc_active>;

arch/arm64/boot/dts/qcom/sdm845-sde-display.dtsi

+11 −1
Original line number Diff line number Diff line
@@ -411,7 +411,17 @@ 


		qcom,dp-usbpd-detection = <&pmi8998_pdphy>;



		qcom,aux-cfg-settings = [00 13 04 00 0a 26 0a 03 bb 03];

		qcom,aux-cfg0-settings = [20 00];

		qcom,aux-cfg1-settings = [24 13 23 1d];

		qcom,aux-cfg2-settings = [28 24];

		qcom,aux-cfg3-settings = [2c 00];

		qcom,aux-cfg4-settings = [30 0a];

		qcom,aux-cfg5-settings = [34 26];

		qcom,aux-cfg6-settings = [38 0a];

		qcom,aux-cfg7-settings = [3c 03];

		qcom,aux-cfg8-settings = [40 bb];

		qcom,aux-cfg9-settings = [44 03];



		qcom,max-pclk-frequency-khz = <576000>;



		qcom,core-supply-entries {

drivers/gpu/drm/msm/dp/dp_aux.c

+11 −2
Original line number Diff line number Diff line
@@ -296,11 +296,19 @@ static ssize_t dp_aux_transfer(struct drm_dp_aux *drm_aux, 
	return ret;

}



static void dp_aux_init(struct dp_aux *dp_aux, u32 *aux_cfg)

static void dp_aux_reset_phy_config_indices(struct dp_aux_cfg *aux_cfg)

{

	int i = 0;



	for (i = 0; i < PHY_AUX_CFG_MAX; i++)

		aux_cfg[i].current_index = 0;

}



static void dp_aux_init(struct dp_aux *dp_aux, struct dp_aux_cfg *aux_cfg)

{

	struct dp_aux_private *aux;



	if (!dp_aux) {

	if (!dp_aux || !aux_cfg) {

		pr_err("invalid input\n");

		return;

	}
@@ -309,6 +317,7 @@ static void dp_aux_init(struct dp_aux *dp_aux, u32 *aux_cfg) 


	aux->catalog->reset(aux->catalog);

	aux->catalog->enable(aux->catalog, true);

	dp_aux_reset_phy_config_indices(aux_cfg);

	aux->catalog->setup(aux->catalog, aux_cfg);

}

drivers/gpu/drm/msm/dp/dp_aux.h

+1 −1
Original line number Diff line number Diff line
@@ -32,7 +32,7 @@ struct dp_aux { 
	int (*drm_aux_register)(struct dp_aux *aux);

	void (*drm_aux_deregister)(struct dp_aux *aux);

	void (*isr)(struct dp_aux *aux);

	void (*init)(struct dp_aux *aux, u32 *aux_cfg);

	void (*init)(struct dp_aux *aux, struct dp_aux_cfg *aux_cfg);

	void (*deinit)(struct dp_aux *aux);

};

drivers/gpu/drm/msm/dp/dp_catalog.c

+11 −12
Original line number Diff line number Diff line
@@ -364,11 +364,13 @@ static void dp_catalog_aux_enable(struct dp_catalog_aux *aux, bool enable) 
	dp_write(base + DP_AUX_CTRL, aux_ctrl);

}



static void dp_catalog_aux_setup(struct dp_catalog_aux *aux, u32 *aux_cfg)

static void dp_catalog_aux_setup(struct dp_catalog_aux *aux,

		struct dp_aux_cfg *cfg)

{

	struct dp_catalog_private *catalog;

	int i = 0;



	if (!aux || !aux_cfg) {

	if (!aux || !cfg) {

		pr_err("invalid input\n");

		return;

	}
@@ -384,16 +386,13 @@ static void dp_catalog_aux_setup(struct dp_catalog_aux *aux, u32 *aux_cfg) 
		QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x3f);



	/* DP AUX CFG register programming */

	dp_write(catalog->io->phy_io.base + DP_PHY_AUX_CFG0, aux_cfg[0]);

	dp_write(catalog->io->phy_io.base + DP_PHY_AUX_CFG1, aux_cfg[1]);

	dp_write(catalog->io->phy_io.base + DP_PHY_AUX_CFG2, aux_cfg[2]);

	dp_write(catalog->io->phy_io.base + DP_PHY_AUX_CFG3, aux_cfg[3]);

	dp_write(catalog->io->phy_io.base + DP_PHY_AUX_CFG4, aux_cfg[4]);

	dp_write(catalog->io->phy_io.base + DP_PHY_AUX_CFG5, aux_cfg[5]);

	dp_write(catalog->io->phy_io.base + DP_PHY_AUX_CFG6, aux_cfg[6]);

	dp_write(catalog->io->phy_io.base + DP_PHY_AUX_CFG7, aux_cfg[7]);

	dp_write(catalog->io->phy_io.base + DP_PHY_AUX_CFG8, aux_cfg[8]);

	dp_write(catalog->io->phy_io.base + DP_PHY_AUX_CFG9, aux_cfg[9]);

	for (i = 0; i < PHY_AUX_CFG_MAX; i++) {

		pr_debug("%s: offset=0x%08x, value=0x%08x\n",

			dp_phy_aux_config_type_to_string(i),

			cfg[i].offset, cfg[i].lut[cfg[i].current_index]);

		dp_write(catalog->io->phy_io.base + cfg[i].offset,

			cfg[i].lut[cfg[i].current_index]);

	}



	dp_write(catalog->io->phy_io.base + DP_PHY_AUX_INTERRUPT_MASK, 0x1F);

}