Merge master.kernel.org:/pub/scm/linux/kernel/git/gregkh/i2c-2.6

Supported chips:

  * IT8705F

    Prefix: 'it87'

    Addresses scanned: from Super I/O config space, or default ISA 0x290 (8 I/O ports)

    Addresses scanned: from Super I/O config space (8 I/O ports)

    Datasheet: Publicly available at the ITE website

               http://www.ite.com.tw/

  * IT8712F

    Prefix: 'it8712'

    Addresses scanned: I2C 0x28 - 0x2f

                       from Super I/O config space, or default ISA 0x290 (8 I/O ports)

                       from Super I/O config space (8 I/O ports)

    Datasheet: Publicly available at the ITE website

               http://www.ite.com.tw/

  * SiS950   [clone of IT8705F]

    Prefix: 'sis950'

    Addresses scanned: from Super I/O config space, or default ISA 0x290 (8 I/O ports)

    Prefix: 'it87'

    Addresses scanned: from Super I/O config space (8 I/O ports)

    Datasheet: No longer be available

Author: Christophe Gauthron <chrisg@0-in.com>

               http://www.national.com/pf/LM/LM86.html

  * Analog Devices ADM1032

    Prefix: 'adm1032'

    Addresses scanned: I2C 0x4c

    Addresses scanned: I2C 0x4c and 0x4d

    Datasheet: Publicly available at the Analog Devices website

               http://products.analog.com/products/info.asp?product=ADM1032

               http://www.analog.com/en/prod/0,2877,ADM1032,00.html

  * Analog Devices ADT7461

    Prefix: 'adt7461'

    Addresses scanned: I2C 0x4c

    Addresses scanned: I2C 0x4c and 0x4d

    Datasheet: Publicly available at the Analog Devices website

               http://products.analog.com/products/info.asp?product=ADT7461

               http://www.analog.com/en/prod/0,2877,ADT7461,00.html

    Note: Only if in ADM1032 compatibility mode

  * Maxim MAX6657

    Prefix: 'max6657'

The different chipsets of the family are not strictly identical, although

very similar. This driver doesn't handle any specific feature for now,

but could if there ever was a need for it. For reference, here comes a

non-exhaustive list of specific features:

with the exception of SMBus PEC. For reference, here comes a non-exhaustive

list of specific features:

LM90:

  * Filter and alert configuration register at 0xBF.

  * Conversion averaging.

  * Up to 64 conversions/s.

  * ALERT is triggered by open remote sensor.

  * SMBus PEC support for Write Byte and Receive Byte transactions.

ADT7461

  * Extended temperature range (breaks compatibility)

other second; reading them more often will do no harm, but will return

'old' values.

PEC Support

-----------

The ADM1032 is the only chip of the family which supports PEC. It does

not support PEC on all transactions though, so some care must be taken.

When reading a register value, the PEC byte is computed and sent by the

ADM1032 chip. However, in the case of a combined transaction (SMBus Read

Byte), the ADM1032 computes the CRC value over only the second half of

the message rather than its entirety, because it thinks the first half

of the message belongs to a different transaction. As a result, the CRC

value differs from what the SMBus master expects, and all reads fail.

For this reason, the lm90 driver will enable PEC for the ADM1032 only if

the bus supports the SMBus Send Byte and Receive Byte transaction types.

These transactions will be used to read register values, instead of

SMBus Read Byte, and PEC will work properly.

Additionally, the ADM1032 doesn't support SMBus Send Byte with PEC.

Instead, it will try to write the PEC value to the register (because the

SMBus Send Byte transaction with PEC is similar to a Write Byte transaction

without PEC), which is not what we want. Thus, PEC is explicitely disabled

on SMBus Send Byte transactions in the lm90 driver.

PEC on byte data transactions represents a significant increase in bandwidth

usage (+33% for writes, +25% for reads) in normal conditions. With the need

to use two SMBus transaction for reads, this overhead jumps to +50%. Worse,

two transactions will typically mean twice as much delay waiting for

transaction completion, effectively doubling the register cache refresh time.

I guess reliability comes at a price, but it's quite expensive this time.

So, as not everyone might enjoy the slowdown, PEC can be disabled through

sysfs. Just write 0 to the "pec" file and PEC will be disabled. Write 1

to that file to enable PEC again.

Supported chips:

  * SMSC LPC47B397-NC

  * SMSC SCH5307-NS

    Prefix: 'smsc47b397'

    Addresses scanned: none, address read from Super I/O config space

    Datasheet: In this file

November 23, 2004

The following specification describes the SMSC LPC47B397-NC sensor chip

The following specification describes the SMSC LPC47B397-NC[1] sensor chip

(for which there is no public datasheet available). This document was

provided by Craig Kelly (In-Store Broadcast Network) and edited/corrected

by Mark M. Hoffman <mhoffman@lightlink.com>.

[1] And SMSC SCH5307-NS, which has a different device ID but is otherwise

compatible.

* * * * *

Methods for detecting the HP SIO and reading the thermal data on a dc7100.

The registers of interest for identifying the SIO on the dc7100 are Device ID

(0x20) and Device Rev  (0x21).

The Device ID will read 0X6F

The Device ID will read 0x6F (for SCH5307-NS, 0x81)

The Device Rev currently reads 0x01

Obtaining the HWM Base Address.

        http://www.smsc.com/main/datasheets/47m14x.pdf

        http://www.smsc.com/main/tools/discontinued/47m15x.pdf

        http://www.smsc.com/main/datasheets/47m192.pdf

  * SMSC LPC47M997

    Addresses scanned: none, address read from Super I/O config space

    Prefix: 'smsc47m1'

    Datasheet: none

Authors:

        Mark D. Studebaker <mdsxyz123@yahoo.com>,

in addition to the fan monitoring and control. The hardware monitoring

block is not supported by the driver.

No documentation is available for the 47M997, but it has the same device

ID as the 47M15x and 47M192 chips and seems to be compatible.

Fan rotation speeds are reported in RPM (rotations per minute). An alarm is

triggered if the rotation speed has dropped below a programmable limit. Fan

readings can be divided by a programmable divider (1, 2, 4 or 8) to give

eeprom		Raw EEPROM data in binary form.

		Read only.

pec		Enable or disable PEC (SMBus only)

		Read/Write