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Commit 201a72b2 authored by Ashok Kumar's avatar Ashok Kumar Committed by Will Deacon
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arm64/perf: Add Broadcom Vulcan PMU support 



Broadcom Vulcan uses ARMv8 PMUv3 and supports most of
the ARMv8 recommended implementation defined events.

Added Vulcan events mapping for perf and perf_cache map.

Acked-by: default avatarMark Rutland <mark.rutland@arm.com>
Signed-off-by: default avatarAshok Kumar <ashoks@broadcom.com>
Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
parent 4b1a9e69

arch/arm64/kernel/perf_event.c

+60 −0
Original line number Diff line number Diff line
@@ -234,6 +234,20 @@ static const unsigned armv8_thunder_perf_map[PERF_COUNT_HW_MAX] = { 
	[PERF_COUNT_HW_STALLED_CYCLES_BACKEND]	= ARMV8_PMUV3_PERFCTR_STALL_BACKEND,

};



/* Broadcom Vulcan events mapping */

static const unsigned armv8_vulcan_perf_map[PERF_COUNT_HW_MAX] = {

	PERF_MAP_ALL_UNSUPPORTED,

	[PERF_COUNT_HW_CPU_CYCLES]		= ARMV8_PMUV3_PERFCTR_CPU_CYCLES,

	[PERF_COUNT_HW_INSTRUCTIONS]		= ARMV8_PMUV3_PERFCTR_INST_RETIRED,

	[PERF_COUNT_HW_CACHE_REFERENCES]	= ARMV8_PMUV3_PERFCTR_L1D_CACHE,

	[PERF_COUNT_HW_CACHE_MISSES]		= ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL,

	[PERF_COUNT_HW_BRANCH_INSTRUCTIONS]	= ARMV8_PMUV3_PERFCTR_BR_RETIRED,

	[PERF_COUNT_HW_BRANCH_MISSES]		= ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,

	[PERF_COUNT_HW_BUS_CYCLES]		= ARMV8_PMUV3_PERFCTR_BUS_CYCLES,

	[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND]	= ARMV8_PMUV3_PERFCTR_STALL_FRONTEND,

	[PERF_COUNT_HW_STALLED_CYCLES_BACKEND]	= ARMV8_PMUV3_PERFCTR_STALL_BACKEND,

};



static const unsigned armv8_pmuv3_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]

						[PERF_COUNT_HW_CACHE_OP_MAX]

						[PERF_COUNT_HW_CACHE_RESULT_MAX] = {
@@ -326,6 +340,35 @@ static const unsigned armv8_thunder_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] 
	[C(BPU)][C(OP_WRITE)][C(RESULT_MISS)]	= ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,

};



static const unsigned armv8_vulcan_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]

					      [PERF_COUNT_HW_CACHE_OP_MAX]

					      [PERF_COUNT_HW_CACHE_RESULT_MAX] = {

	PERF_CACHE_MAP_ALL_UNSUPPORTED,



	[C(L1D)][C(OP_READ)][C(RESULT_ACCESS)]	= ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD,

	[C(L1D)][C(OP_READ)][C(RESULT_MISS)]	= ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_RD,

	[C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)]	= ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR,

	[C(L1D)][C(OP_WRITE)][C(RESULT_MISS)]	= ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_WR,



	[C(L1I)][C(OP_READ)][C(RESULT_ACCESS)]	= ARMV8_PMUV3_PERFCTR_L1I_CACHE,

	[C(L1I)][C(OP_READ)][C(RESULT_MISS)]	= ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL,



	[C(ITLB)][C(OP_READ)][C(RESULT_MISS)]	= ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL,

	[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)]	= ARMV8_PMUV3_PERFCTR_L1I_TLB,



	[C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)]	= ARMV8_IMPDEF_PERFCTR_L1D_TLB_RD,

	[C(DTLB)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_WR,

	[C(DTLB)][C(OP_READ)][C(RESULT_MISS)]	= ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD,

	[C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)]	= ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR,



	[C(BPU)][C(OP_READ)][C(RESULT_ACCESS)]	= ARMV8_PMUV3_PERFCTR_BR_PRED,

	[C(BPU)][C(OP_READ)][C(RESULT_MISS)]	= ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,

	[C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)]	= ARMV8_PMUV3_PERFCTR_BR_PRED,

	[C(BPU)][C(OP_WRITE)][C(RESULT_MISS)]	= ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,



	[C(NODE)][C(OP_READ)][C(RESULT_ACCESS)]	= ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_RD,

	[C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_WR,

};



static ssize_t

armv8pmu_events_sysfs_show(struct device *dev,
@@ -889,6 +932,13 @@ static int armv8_thunder_map_event(struct perf_event *event) 
				ARMV8_PMU_EVTYPE_EVENT);

}



static int armv8_vulcan_map_event(struct perf_event *event)

{

	return armpmu_map_event(event, &armv8_vulcan_perf_map,

				&armv8_vulcan_perf_cache_map,

				ARMV8_PMU_EVTYPE_EVENT);

}



static void __armv8pmu_probe_pmu(void *info)

{

	struct arm_pmu *cpu_pmu = info;
@@ -976,12 +1026,22 @@ static int armv8_thunder_pmu_init(struct arm_pmu *cpu_pmu) 
	return armv8pmu_probe_pmu(cpu_pmu);

}



static int armv8_vulcan_pmu_init(struct arm_pmu *cpu_pmu)

{

	armv8_pmu_init(cpu_pmu);

	cpu_pmu->name			= "armv8_brcm_vulcan";

	cpu_pmu->map_event		= armv8_vulcan_map_event;

	cpu_pmu->pmu.attr_groups	= armv8_pmuv3_attr_groups;

	return armv8pmu_probe_pmu(cpu_pmu);

}



static const struct of_device_id armv8_pmu_of_device_ids[] = {

	{.compatible = "arm,armv8-pmuv3",	.data = armv8_pmuv3_init},

	{.compatible = "arm,cortex-a53-pmu",	.data = armv8_a53_pmu_init},

	{.compatible = "arm,cortex-a57-pmu",	.data = armv8_a57_pmu_init},

	{.compatible = "arm,cortex-a72-pmu",	.data = armv8_a72_pmu_init},

	{.compatible = "cavium,thunder-pmu",	.data = armv8_thunder_pmu_init},

	{.compatible = "brcm,vulcan-pmu",	.data = armv8_vulcan_pmu_init},

	{},

};