Merge "iommu/arm-smmu: Wire up generic configuration support" into msm-4.8 (1fcb5ca2) · Commits · e / devices / android_kernel_fairphone_FP3

drivers/iommu/arm-smmu.c

+110 −59

Original line number	Diff line number	Diff line
		@@ -517,6 +517,8 @@ struct arm_smmu_option_prop {

		static atomic_t cavium_smmu_context_count = ATOMIC_INIT(0);

		static bool using_legacy_binding, using_generic_binding;

		static struct arm_smmu_option_prop arm_smmu_options[] = {
		{ ARM_SMMU_OPT_SECURE_CFG_ACCESS, "calxeda,smmu-secure-config-access" },
		{ ARM_SMMU_OPT_FATAL_ASF, "qcom,fatal-asf" },
		@@ -1488,12 +1490,6 @@ static int arm_smmu_init_domain_context(struct iommu_domain *domain,
		smmu_domain->cfg.irptndx = INVALID_IRPTNDX;
		smmu_domain->cfg.asid = INVALID_ASID;

		/* We're bypassing these SIDs, so don't allocate an actual context */
		if (domain->type == IOMMU_DOMAIN_DMA) {
		smmu_domain->smmu = smmu;
		goto out_unlock;
		}

		dynamic = is_dynamic_domain(domain);
		if (dynamic && !(smmu->options & ARM_SMMU_OPT_DYNAMIC)) {
		dev_err(smmu->dev, "dynamic domains not supported\n");
		@@ -1698,7 +1694,7 @@ static void arm_smmu_destroy_domain_context(struct iommu_domain *domain)
		bool dynamic;
		int ret;

		if (!smmu \|\| domain->type == IOMMU_DOMAIN_DMA)
		if (!smmu)
		return;

		ret = arm_smmu_power_on(smmu->pwr);
		@@ -1760,8 +1756,8 @@ static struct iommu_domain *arm_smmu_domain_alloc(unsigned type)
		if (!smmu_domain)
		return NULL;

		if (type == IOMMU_DOMAIN_DMA &&
		iommu_get_dma_cookie(&smmu_domain->domain)) {
		if (type == IOMMU_DOMAIN_DMA && (using_legacy_binding \|\|
		iommu_get_dma_cookie(&smmu_domain->domain))) {
		kfree(smmu_domain);
		return NULL;
		}
		@@ -1883,19 +1879,22 @@ static int arm_smmu_master_alloc_smes(struct device *dev)
		mutex_lock(&smmu->stream_map_mutex);
		/* Figure out a viable stream map entry allocation */
		for_each_cfg_sme(fwspec, i, idx) {
		u16 sid = fwspec->ids[i];
		u16 mask = fwspec->ids[i] >> SMR_MASK_SHIFT;

		if (idx != INVALID_SMENDX) {
		ret = -EEXIST;
		goto out_err;
		}

		ret = arm_smmu_find_sme(smmu, fwspec->ids[i], 0);
		ret = arm_smmu_find_sme(smmu, sid, mask);
		if (ret < 0)
		goto out_err;

		idx = ret;
		if (smrs && smmu->s2crs[idx].count == 0) {
		smrs[idx].id = fwspec->ids[i];
		smrs[idx].mask = 0; /* We don't currently share SMRs */
		smrs[idx].id = sid;
		smrs[idx].mask = mask;
		smrs[idx].valid = true;
		}
		smmu->s2crs[idx].count++;
		@@ -1953,15 +1952,6 @@ static int arm_smmu_domain_add_master(struct arm_smmu_domain *smmu_domain,
		u8 cbndx = smmu_domain->cfg.cbndx;
		int i, idx;

		/*
		* FIXME: This won't be needed once we have IOMMU-backed DMA ops
		* for all devices behind the SMMU. Note that we need to take
		* care configuring SMRs for devices both a platform_device and
		* and a PCI device (i.e. a PCI host controller)
		*/
		if (smmu_domain->domain.type == IOMMU_DOMAIN_DMA)
		type = S2CR_TYPE_BYPASS;

		for_each_cfg_sme(fwspec, i, idx) {
		if (type == s2cr[idx].type && cbndx == s2cr[idx].cbndx)
		continue;
		@@ -2337,27 +2327,54 @@ static bool arm_smmu_capable(enum iommu_cap cap)
		}
		}

		static int arm_smmu_match_node(struct device dev, void data)
		{
		return dev->of_node == data;
		}

		static struct arm_smmu_device arm_smmu_get_by_node(struct device_node np)
		{
		struct device *dev = driver_find_device(&arm_smmu_driver.driver, NULL,
		np, arm_smmu_match_node);
		put_device(dev);
		return dev ? dev_get_drvdata(dev) : NULL;
		}

		static int arm_smmu_add_device(struct device *dev)
		{
		struct arm_smmu_device *smmu;
		struct arm_smmu_master_cfg *cfg;
		struct iommu_fwspec *fwspec;
		struct iommu_fwspec *fwspec = dev->iommu_fwspec;
		int i, ret;

		if (using_legacy_binding) {
		ret = arm_smmu_register_legacy_master(dev, &smmu);
		fwspec = dev->iommu_fwspec;
		if (ret)
		goto out_free;
		} else if (fwspec) {
		smmu = arm_smmu_get_by_node(to_of_node(fwspec->iommu_fwnode));
		if (!smmu)
		return -ENODEV;
		} else {
		return -ENODEV;
		}

		ret = -EINVAL;
		for (i = 0; i < fwspec->num_ids; i++) {
		u16 sid = fwspec->ids[i];
		u16 mask = fwspec->ids[i] >> SMR_MASK_SHIFT;

		if (sid & ~smmu->streamid_mask) {
		dev_err(dev, "stream ID 0x%x out of range for SMMU (0x%x)\n",
		sid, smmu->streamid_mask);
		goto out_free;
		}
		if (mask & ~smmu->smr_mask_mask) {
		dev_err(dev, "SMR mask 0x%x out of range for SMMU (0x%x)\n",
		sid, smmu->smr_mask_mask);
		goto out_free;
		}
		}

		ret = -ENOMEM;
		@@ -2658,6 +2675,19 @@ static int arm_smmu_domain_set_attr(struct iommu_domain *domain,
		return ret;
		}

		static int arm_smmu_of_xlate(struct device dev, struct of_phandle_args args)
		{
		u32 fwid = 0;

		if (args->args_count > 0)
		fwid \|= (u16)args->args[0];

		if (args->args_count > 1)
		fwid \|= (u16)args->args[1] << SMR_MASK_SHIFT;

		return iommu_fwspec_add_ids(dev, &fwid, 1);
		}

		static void arm_smmu_trigger_fault(struct iommu_domain *domain,
		unsigned long flags)
		{
		@@ -2779,6 +2809,7 @@ static struct iommu_ops arm_smmu_ops = {
		.device_group = arm_smmu_device_group,
		.domain_get_attr = arm_smmu_domain_get_attr,
		.domain_set_attr = arm_smmu_domain_set_attr,
		.of_xlate = arm_smmu_of_xlate,
		.pgsize_bitmap = -1UL, /* Restricted during device attach */
		.trigger_fault = arm_smmu_trigger_fault,
		.reg_read = arm_smmu_reg_read,
		@@ -3547,6 +3578,19 @@ static int arm_smmu_device_dt_probe(struct platform_device *pdev)
		struct arm_smmu_device *smmu;
		struct device *dev = &pdev->dev;
		int num_irqs, i, err;
		bool legacy_binding;

		legacy_binding = of_find_property(dev->of_node, "mmu-masters", NULL);
		if (legacy_binding && !using_generic_binding) {
		if (!using_legacy_binding)
		pr_notice("deprecated \"mmu-masters\" DT property in use; DMA API support unavailable\n");
		using_legacy_binding = true;
		} else if (!legacy_binding && !using_legacy_binding) {
		using_generic_binding = true;
		} else {
		dev_err(dev, "not probing due to mismatched DT properties\n");
		return -ENODEV;
		}

		smmu = devm_kzalloc(dev, sizeof(*smmu), GFP_KERNEL);
		if (!smmu) {
		@@ -3653,6 +3697,19 @@ static int arm_smmu_device_dt_probe(struct platform_device *pdev)
		arm_smmu_device_reset(smmu);
		arm_smmu_power_off(smmu->pwr);

		/* Oh, for a proper bus abstraction */
		if (!iommu_present(&platform_bus_type))
		bus_set_iommu(&platform_bus_type, &arm_smmu_ops);
		#ifdef CONFIG_ARM_AMBA
		if (!iommu_present(&amba_bustype))
		bus_set_iommu(&amba_bustype, &arm_smmu_ops);
		#endif
		#ifdef CONFIG_PCI
		if (!iommu_present(&pci_bus_type)) {
		pci_request_acs();
		bus_set_iommu(&pci_bus_type, &arm_smmu_ops);
		}
		#endif
		return 0;

		out_power_off:
		@@ -3699,41 +3756,14 @@ static struct platform_driver arm_smmu_driver = {

		static int __init arm_smmu_init(void)
		{
		struct device_node *np;
		int ret;

		/*
		* Play nice with systems that don't have an ARM SMMU by checking that
		* an ARM SMMU exists in the system before proceeding with the driver
		* and IOMMU bus operation registration.
		*/
		np = of_find_matching_node(NULL, arm_smmu_of_match);
		if (!np)
		return 0;

		of_node_put(np);
		static bool registered;
		int ret = 0;

		if (!registered) {
		ret = platform_driver_register(&arm_smmu_driver);
		if (ret)
		return ret;

		/* Oh, for a proper bus abstraction */
		if (!iommu_present(&platform_bus_type))
		bus_set_iommu(&platform_bus_type, &arm_smmu_ops);

		#ifdef CONFIG_ARM_AMBA
		if (!iommu_present(&amba_bustype))
		bus_set_iommu(&amba_bustype, &arm_smmu_ops);
		#endif

		#ifdef CONFIG_PCI
		if (!iommu_present(&pci_bus_type)) {
		pci_request_acs();
		bus_set_iommu(&pci_bus_type, &arm_smmu_ops);
		registered = !ret;
		}
		#endif

		return 0;
		return ret;
		}

		static void __exit arm_smmu_exit(void)
		@@ -3744,6 +3774,27 @@ static void __exit arm_smmu_exit(void)
		subsys_initcall(arm_smmu_init);
		module_exit(arm_smmu_exit);

		static int __init arm_smmu_of_init(struct device_node *np)
		{
		int ret = arm_smmu_init();

		if (ret)
		return ret;

		if (!of_platform_device_create(np, NULL, platform_bus_type.dev_root))
		return -ENODEV;

		return 0;
		}
		IOMMU_OF_DECLARE(arm_smmuv1, "arm,smmu-v1", arm_smmu_of_init);
		IOMMU_OF_DECLARE(arm_smmuv2, "arm,smmu-v2", arm_smmu_of_init);
		IOMMU_OF_DECLARE(arm_mmu400, "arm,mmu-400", arm_smmu_of_init);
		IOMMU_OF_DECLARE(arm_mmu401, "arm,mmu-401", arm_smmu_of_init);
		IOMMU_OF_DECLARE(arm_mmu500, "arm,mmu-500", arm_smmu_of_init);
		IOMMU_OF_DECLARE(cavium_smmuv2, "cavium,smmu-v2", arm_smmu_of_init);
		IOMMU_OF_DECLARE(qcom_smmuv2, "qcom,smmu-v2", arm_smmu_of_init);
		IOMMU_OF_DECLARE(qcom_mmu500, "qcom,qsmmu-v500", arm_smmu_of_init);

		#define DEBUG_SID_HALT_REG 0x0
		#define DEBUG_SID_HALT_VAL (0x1 << 16)