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Commit 1fb32ea7 authored by Lloyd Atkinson's avatar Lloyd Atkinson
Browse files

drm/msm/sde: request affine cores mask from pm_qos 



Add support for requesting a cpu dma latency QoS level from
pm_qos to hold desired cores at a particular QoS level.

Change-Id: Idee01f19af4c8c9e235e0b1a177cd0602847c9dc
Signed-off-by: default avatarLloyd Atkinson <latkinso@codeaurora.org>
parent f5075bad

Documentation/devicetree/bindings/display/msm/sde.txt

+5 −0
Original line number Diff line number Diff line
@@ -366,6 +366,8 @@ Optional properties: 
- qcom,sde-cdp-setting:		Array of 2 cell property, with a format of

				<read enable, write enable> for cdp use cases in

				order of <real_time>, and <non_real_time>.

- qcom,sde-qos-cpu-mask:	A u32 value indicating desired PM QoS CPU affine mask.

- qcom,sde-qos-cpu-dma-latency:	A u32 value indicating desired PM QoS CPU DMA latency in usec.

- qcom,sde-inline-rot-xin:	An integer array of xin-ids related to inline

				rotation.

- qcom,sde-inline-rot-xin-type:	A string array indicating the type of xin,
@@ -611,6 +613,9 @@ Example: 


    qcom,sde-cdp-setting = <1 1>, <1 0>;



    qcom,sde-qos-cpu-mask = <0x3>;

    qcom,sde-qos-cpu-dma-latency = <300>;



    qcom,sde-vbif-off = <0 0>;

    qcom,sde-vbif-id = <0 1>;

    qcom,sde-vbif-default-ot-rd-limit = <32>;

drivers/gpu/drm/msm/sde/sde_hw_catalog.c

+17 −0
Original line number Diff line number Diff line
@@ -15,6 +15,7 @@ 
#include <linux/of_address.h>

#include <linux/platform_device.h>

#include <linux/soc/qcom/llcc-qcom.h>

#include <linux/pm_qos.h>



#include "sde_hw_mdss.h"

#include "sde_hw_catalog.h"
@@ -115,6 +116,8 @@ 
		"NV12/5/1/1.25 AB24/5/1/1.25 XB24/5/1/1.25"

#define DEFAULT_MAX_PER_PIPE_BW			2400000

#define DEFAULT_AMORTIZABLE_THRESHOLD		25

#define DEFAULT_CPU_MASK			0

#define DEFAULT_CPU_DMA_LATENCY			PM_QOS_DEFAULT_VALUE



/*************************************************************

 *  DTSI PROPERTY INDEX
@@ -176,6 +179,8 @@ enum { 
	PERF_QOS_LUT_NRT,

	PERF_QOS_LUT_CWB,

	PERF_CDP_SETTING,

	PERF_CPU_MASK,

	PERF_CPU_DMA_LATENCY,

	PERF_PROP_MAX,

};
@@ -448,6 +453,9 @@ static struct sde_prop_type sde_perf_prop[] = { 


	{PERF_CDP_SETTING, "qcom,sde-cdp-setting", false,

			PROP_TYPE_U32_ARRAY},

	{PERF_CPU_MASK, "qcom,sde-qos-cpu-mask", false, PROP_TYPE_U32},

	{PERF_CPU_DMA_LATENCY, "qcom,sde-qos-cpu-dma-latency", false,

			PROP_TYPE_U32},

};



static struct sde_prop_type sspp_prop[] = {
@@ -3083,6 +3091,15 @@ static int sde_perf_parse_dt(struct device_node *np, struct sde_mdss_cfg *cfg) 
		cfg->has_cdp = true;

	}



	cfg->perf.cpu_mask =

			prop_exists[PERF_CPU_MASK] ?

			PROP_VALUE_ACCESS(prop_value, PERF_CPU_MASK, 0) :

			DEFAULT_CPU_MASK;

	cfg->perf.cpu_dma_latency =

			prop_exists[PERF_CPU_DMA_LATENCY] ?

			PROP_VALUE_ACCESS(prop_value, PERF_CPU_DMA_LATENCY, 0) :

			DEFAULT_CPU_DMA_LATENCY;



freeprop:

	kfree(prop_value);

end:

drivers/gpu/drm/msm/sde/sde_hw_catalog.h

+4 −0
Original line number Diff line number Diff line
@@ -866,6 +866,8 @@ struct sde_perf_cdp_cfg { 
 * @sfe_lut_tbl: LUT tables for safe signals

 * @qos_lut_tbl: LUT tables for QoS signals

 * @cdp_cfg            cdp use case configurations

 * @cpu_mask:          pm_qos cpu mask value

 * @cpu_dma_latency:   pm_qos cpu dma latency value

 */

struct sde_perf_cfg {

	u32 max_bw_low;
@@ -890,6 +892,8 @@ struct sde_perf_cfg { 
	struct sde_qos_lut_tbl sfe_lut_tbl[SDE_QOS_LUT_USAGE_MAX];

	struct sde_qos_lut_tbl qos_lut_tbl[SDE_QOS_LUT_USAGE_MAX];

	struct sde_perf_cdp_cfg cdp_cfg[SDE_PERF_CDP_USAGE_MAX];

	u32 cpu_mask;

	u32 cpu_dma_latency;

};



/**

drivers/gpu/drm/msm/sde/sde_kms.c

+37 −0
Original line number Diff line number Diff line
@@ -2229,6 +2229,41 @@ static int _sde_kms_mmu_init(struct sde_kms *sde_kms) 
	return ret;

}



static void _sde_kms_pm_qos_add_request(struct sde_kms *sde_kms)

{

	struct pm_qos_request *req;

	u32 cpu_mask;

	u32 cpu_dma_latency;

	int cpu;



	if (!sde_kms || !sde_kms->catalog)

		return;



	cpu_mask = sde_kms->catalog->perf.cpu_mask;

	cpu_dma_latency = sde_kms->catalog->perf.cpu_dma_latency;

	if (!cpu_mask)

		return;



	req = &sde_kms->pm_qos_cpu_req;

	req->type = PM_QOS_REQ_AFFINE_CORES;

	cpumask_empty(&req->cpus_affine);

	for_each_possible_cpu(cpu) {

		if ((1 << cpu) & cpu_mask)

			cpumask_set_cpu(cpu, &req->cpus_affine);

	}

	pm_qos_add_request(req, PM_QOS_CPU_DMA_LATENCY, cpu_dma_latency);



	SDE_EVT32_VERBOSE(cpu_mask, cpu_dma_latency);

}



static void _sde_kms_pm_qos_remove_request(struct sde_kms *sde_kms)

{

	if (!sde_kms || !sde_kms->catalog || !sde_kms->catalog->perf.cpu_mask)

		return;



	pm_qos_remove_request(&sde_kms->pm_qos_cpu_req);

}



static void sde_kms_handle_power_event(u32 event_type, void *usr)

{

	struct sde_kms *sde_kms = usr;
@@ -2244,7 +2279,9 @@ static void sde_kms_handle_power_event(u32 event_type, void *usr) 
	if (event_type == SDE_POWER_EVENT_POST_ENABLE) {

		sde_irq_update(msm_kms, true);

		sde_vbif_init_memtypes(sde_kms);

		_sde_kms_pm_qos_add_request(sde_kms);

	} else if (event_type == SDE_POWER_EVENT_PRE_DISABLE) {

		_sde_kms_pm_qos_remove_request(sde_kms);

		sde_irq_update(msm_kms, false);

	}

}

drivers/gpu/drm/msm/sde/sde_kms.h

+2 −0
Original line number Diff line number Diff line
@@ -21,6 +21,7 @@ 


#include <linux/msm_ion.h>

#include <linux/pm_domain.h>

#include <linux/pm_qos.h>



#include "msm_drv.h"

#include "msm_kms.h"
@@ -182,6 +183,7 @@ struct sde_kms { 


	struct msm_gem_address_space *aspace[MSM_SMMU_DOMAIN_MAX];

	struct sde_power_client *core_client;

	struct pm_qos_request pm_qos_cpu_req;



	struct ion_client *iclient;

	struct sde_power_event *power_event;