Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 1f9a99e0 authored by Michel Thierry's avatar Michel Thierry Committed by Daniel Vetter
Browse files

drm/i915/gen8: Flip the 48b switch 



Use 48b addresses if hw supports it (i915.enable_ppgtt=3).
Update the sanitize_enable_ppgtt for 48 bit PPGTT mode.

Note, aliasing PPGTT remains 32b only.

v2: s/full_64b/full_48b/. (Akash)
v3: Add sanitize_enable_ppgtt changes until here. (Akash)
v4: Update param description (Chris)

Cc: Akash Goel <akash.goel@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: default avatarMichel Thierry <michel.thierry@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 6173ee28

drivers/gpu/drm/i915/i915_gem_gtt.c

+6 −1
Original line number Original line Diff line number Diff line
@@ -104,9 +104,11 @@ static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt) 
{

{

	bool has_aliasing_ppgtt;

	bool has_aliasing_ppgtt;

	bool has_full_ppgtt;

	bool has_full_ppgtt;

	bool has_full_48bit_ppgtt;





	has_aliasing_ppgtt = INTEL_INFO(dev)->gen >= 6;

	has_aliasing_ppgtt = INTEL_INFO(dev)->gen >= 6;

	has_full_ppgtt = INTEL_INFO(dev)->gen >= 7;

	has_full_ppgtt = INTEL_INFO(dev)->gen >= 7;

	has_full_48bit_ppgtt = IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9;





	if (intel_vgpu_active(dev))

	if (intel_vgpu_active(dev))

		has_full_ppgtt = false; /* emulation is too hard */

		has_full_ppgtt = false; /* emulation is too hard */
@@ -125,6 +127,9 @@ static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt) 
	if (enable_ppgtt == 2 && has_full_ppgtt)

	if (enable_ppgtt == 2 && has_full_ppgtt)

		return 2;

		return 2;





	if (enable_ppgtt == 3 && has_full_48bit_ppgtt)

		return 3;



#ifdef CONFIG_INTEL_IOMMU

#ifdef CONFIG_INTEL_IOMMU

	/* Disable ppgtt on SNB if VT-d is on. */

	/* Disable ppgtt on SNB if VT-d is on. */

	if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) {

	if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) {
@@ -141,7 +146,7 @@ static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt) 
	}

	}





	if (INTEL_INFO(dev)->gen >= 8 && i915.enable_execlists)

	if (INTEL_INFO(dev)->gen >= 8 && i915.enable_execlists)

		return 2;

		return has_full_48bit_ppgtt ? 3 : 2;

	else

	else

		return has_aliasing_ppgtt ? 1 : 0;

		return has_aliasing_ppgtt ? 1 : 0;

}

}

drivers/gpu/drm/i915/i915_params.c

+1 −1
Original line number Original line Diff line number Diff line
@@ -111,7 +111,7 @@ MODULE_PARM_DESC(enable_hangcheck, 
module_param_named_unsafe(enable_ppgtt, i915.enable_ppgtt, int, 0400);

module_param_named_unsafe(enable_ppgtt, i915.enable_ppgtt, int, 0400);

MODULE_PARM_DESC(enable_ppgtt,

MODULE_PARM_DESC(enable_ppgtt,

	"Override PPGTT usage. "

	"Override PPGTT usage. "

	"(-1=auto [default], 0=disabled, 1=aliasing, 2=full)");

	"(-1=auto [default], 0=disabled, 1=aliasing, 2=full, 3=full with extended address space)");





module_param_named_unsafe(enable_execlists, i915.enable_execlists, int, 0400);

module_param_named_unsafe(enable_execlists, i915.enable_execlists, int, 0400);

MODULE_PARM_DESC(enable_execlists,

MODULE_PARM_DESC(enable_execlists,