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Commit 1f6a4e0a authored by mohamed sunfeer's avatar mohamed sunfeer Committed by Brahmaji K
Browse files

ARM: dts: msm: Add crypto device nodes for sdm450 



Add crypto device nodes with the required configuration
on the include file, which is needed to initialize the
the crypto drivers for sdm450 to perform crypto related
operations.

Change-Id: If09cae1407b78433eff0a68095a0ce9929b17e12
Signed-off-by: default avatarmohamed sunfeer <msunfeer@codeaurora.org>
Signed-off-by: default avatarBrahmaji K <bkomma@codeaurora.org>
parent 0d623228

arch/arm64/boot/dts/qcom/msm8953.dtsi

+59 −0
Original line number Diff line number Diff line
@@ -532,6 +532,65 @@ 
		status = "disabled";

	};



	qcom_crypto: qcrypto@720000 {

		compatible = "qcom,qcrypto";

		reg = <0x720000 0x20000>,

		      <0x704000 0x20000>;

		reg-names = "crypto-base","crypto-bam-base";

		interrupts = <0 207 0>;

		qcom,bam-pipe-pair = <2>;

		qcom,ce-hw-instance = <0>;

		qcom,ce-device = <0>;

		qcom,ce-hw-shared;

		qcom,clk-mgmt-sus-res;

		qcom,msm-bus,name = "qcrypto-noc";

		qcom,msm-bus,num-cases = <2>;

		qcom,msm-bus,num-paths = <1>;

		qcom,msm-bus,vectors-KBps =

				<55 512 0 0>,

				<55 512 393600 393600>;

		clocks = <&clock_gcc clk_crypto_clk_src>,

			 <&clock_gcc clk_gcc_crypto_clk>,

			 <&clock_gcc clk_gcc_crypto_ahb_clk>,

			 <&clock_gcc clk_gcc_crypto_axi_clk>;

		clock-names = "core_clk_src", "core_clk",

				"iface_clk", "bus_clk";

		qcom,use-sw-aes-cbc-ecb-ctr-algo;

		qcom,use-sw-aes-xts-algo;

		qcom,use-sw-aes-ccm-algo;

		qcom,use-sw-ahash-algo;

		qcom,use-sw-hmac-algo;

		qcom,use-sw-aead-algo;

		qcom,ce-opp-freq = <100000000>;

		status = "disabled";

	};



	qcom_cedev: qcedev@720000 {

		compatible = "qcom,qcedev";

		reg = <0x720000 0x20000>,

		      <0x704000 0x20000>;

		reg-names = "crypto-base","crypto-bam-base";

		interrupts = <0 207 0>;

		qcom,bam-pipe-pair = <1>;

		qcom,ce-hw-instance = <0>;

		qcom,ce-device = <0>;

		qcom,ce-hw-shared;

		qcom,msm-bus,name = "qcedev-noc";

		qcom,msm-bus,num-cases = <2>;

		qcom,msm-bus,num-paths = <1>;

		qcom,msm-bus,vectors-KBps =

				<55 512 0 0>,

				<55 512 393600 393600>;

		clocks = <&clock_gcc clk_crypto_clk_src>,

			 <&clock_gcc clk_gcc_crypto_clk>,

			 <&clock_gcc clk_gcc_crypto_ahb_clk>,

			 <&clock_gcc clk_gcc_crypto_axi_clk>;

		clock-names = "core_clk_src", "core_clk",

				"iface_clk", "bus_clk";

		qcom,ce-opp-freq = <100000000>;

		status = "disabled";

	};



	blsp1_uart0: serial@78af000 {

		compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";

		reg = <0x78af000 0x200>;