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Commit 1ec3f937 authored by Paul Mackerras's avatar Paul Mackerras Committed by Michael Ellerman
Browse files

powerpc/mm/book3s-64: Clean up some obsolete or misleading comments 



No code changes.

Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
parent 2527083c

arch/powerpc/include/asm/book3s/64/hash.h

+6 −7
Original line number Diff line number Diff line
@@ -4,8 +4,7 @@ 


/*

 * Common bits between 4K and 64K pages in a linux-style PTE.

 * These match the bits in the (hardware-defined) PowerPC PTE as closely

 * as possible. Additional bits may be defined in pgtable-hash64-*.h

 * Additional bits may be defined in pgtable-hash64-*.h

 *

 * Note: We only support user read/write permissions. Supervisor always

 * have full read/write to pages above PAGE_OFFSET (pages below that
@@ -14,13 +13,13 @@ 
 * We could create separate kernel read-only if we used the 3 PP bits

 * combinations that newer processors provide but we currently don't.

 */

#define _PAGE_PTE		0x00001

#define _PAGE_PTE		0x00001	/* distinguishes PTEs from pointers */

#define _PAGE_PRESENT		0x00002 /* software: pte contains a translation */

#define _PAGE_BIT_SWAP_TYPE	2

#define _PAGE_USER		0x00004 /* matches one of the PP bits */

#define _PAGE_EXEC		0x00008 /* No execute on POWER4 and newer (we invert) */

#define _PAGE_GUARDED		0x00010

/* We can derive Memory coherence from _PAGE_NO_CACHE */

#define _PAGE_USER		0x00004 /* page may be accessed by userspace */

#define _PAGE_EXEC		0x00008 /* execute permission */

#define _PAGE_GUARDED		0x00010 /* G: guarded (side-effect) page */

/* M (memory coherence) is always set in the HPTE, so we don't need it here */

#define _PAGE_COHERENT		0x0

#define _PAGE_NO_CACHE		0x00020 /* I: cache inhibit */

#define _PAGE_WRITETHRU		0x00040 /* W: cache write-through */

arch/powerpc/mm/hash64_64k.c

+1 −2
Original line number Diff line number Diff line
@@ -249,8 +249,7 @@ int __hash_page_64K(unsigned long ea, unsigned long access, 
			return 0;

		/*

		 * Try to lock the PTE, add ACCESSED and DIRTY if it was

		 * a write access. Since this is 4K insert of 64K page size

		 * also add _PAGE_COMBO

		 * a write access.

		 */

		new_pte = old_pte | _PAGE_BUSY | _PAGE_ACCESSED;

		if (access & _PAGE_RW)

arch/powerpc/mm/hash_utils_64.c

+5 −5
Original line number Diff line number Diff line
@@ -168,11 +168,11 @@ unsigned long htab_convert_pte_flags(unsigned long pteflags) 
		rflags |= HPTE_R_N;

	/*

	 * PP bits:

	 * Linux use slb key 0 for kernel and 1 for user.

	 * kernel areas are mapped by PP bits 00

	 * and and there is no kernel RO (_PAGE_KERNEL_RO).

	 * User area mapped by 0x2 and read only use by

	 * 0x3.

	 * Linux uses slb key 0 for kernel and 1 for user.

	 * kernel areas are mapped with PP=00

	 * and there is no kernel RO (_PAGE_KERNEL_RO).

	 * User area is mapped with PP=0x2 for read/write

	 * or PP=0x3 for read-only (including writeable but clean pages).

	 */

	if (pteflags & _PAGE_USER) {

		rflags |= 0x2;