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Commit 1dd64089 authored by Taniya Das's avatar Taniya Das
Browse files

clk: msm: gcc: Add support for GPU clock 700/725MHz 



SDM632 requires gfx client requires to vote on the new frequencies of 700 &
725MHz, so add support for these new frequencies.

Change-Id: I47332ed4467a02b6b01ea6bb69e96a74e4c26932
Signed-off-by: default avatarTaniya Das <tdas@codeaurora.org>
parent b2f7549d

arch/arm64/boot/dts/qcom/sdm632.dtsi

+11 −0
Original line number Diff line number Diff line
@@ -40,6 +40,17 @@ 


&clock_gcc_gfx {

	compatible = "qcom,gcc-gfx-sdm632";

	qcom,gfxfreq-corner =

		 <         0   0 >,

		 < 133330000   1 >,  /* Min SVS   */

		 < 216000000   2 >,  /* Low SVS   */

		 < 320000000   3 >,  /* SVS       */

		 < 400000000   4 >,  /* SVS Plus  */

		 < 510000000   5 >,  /* NOM       */

		 < 560000000   6 >,  /* Nom Plus  */

		 < 650000000   7 >,  /* Turbo     */

		 < 700000000   7 >,  /* Turbo     */

		 < 725000000   7 >;  /* Turbo     */

};



&thermal_zones {

drivers/clk/msm/clock-gcc-8953.c

+26 −0
Original line number Diff line number Diff line
@@ -411,6 +411,27 @@ static struct clk_freq_tbl ftbl_gfx3d_clk_src_sdm450[] = { 
	F_END

};



static struct clk_freq_tbl ftbl_gfx3d_clk_src_sdm632[] = {

	F_MM(  19200000, FIXED_CLK_SRC,                  xo,    1,    0,     0),

	F_MM(  50000000, FIXED_CLK_SRC,  gpll0_main_div2_mm,    8,    0,     0),

	F_MM(  80000000, FIXED_CLK_SRC,  gpll0_main_div2_mm,    5,    0,     0),

	F_MM( 100000000, FIXED_CLK_SRC,  gpll0_main_div2_mm,    4,    0,     0),

	F_MM( 133330000, FIXED_CLK_SRC,  gpll0_main_div2_mm,    3,    0,     0),

	F_MM( 160000000, FIXED_CLK_SRC,  gpll0_main_div2_mm,  2.5,    0,     0),

	F_MM( 200000000, FIXED_CLK_SRC,  gpll0_main_div2_mm,    2,    0,     0),

	F_MM( 216000000, FIXED_CLK_SRC, gpll6_main_div2_gfx,  2.5,    0,     0),

	F_MM( 266670000, FIXED_CLK_SRC,               gpll0,    3,    0,     0),

	F_MM( 320000000, FIXED_CLK_SRC,               gpll0,  2.5,    0,     0),

	F_MM( 400000000, FIXED_CLK_SRC,               gpll0,    2,    0,     0),

	F_MM( 460800000, FIXED_CLK_SRC,       gpll4_out_aux,  2.5,    0,     0),

	F_MM( 510000000,    1020000000,               gpll3,    1,    0,     0),

	F_MM( 560000000,    1120000000,               gpll3,    1,    0,     0),

	F_MM( 650000000,    1300000000,               gpll3,    1,    0,     0),

	F_MM( 700000000,    1400000000,               gpll3,    1,    0,     0),

	F_MM( 725000000,    1450000000,               gpll3,    1,    0,     0),



	F_END

};

static struct rcg_clk gfx3d_clk_src = {

	.cmd_rcgr_reg = GFX3D_CMD_RCGR,

	.set_rate = set_rate_hid,
@@ -4104,6 +4125,11 @@ static int msm_gcc_gfx_probe(struct platform_device *pdev) 
	if (compat_bin)

		gfx3d_clk_src.freq_tbl = ftbl_gfx3d_clk_src_sdm450;



	compat_bin = of_device_is_compatible(pdev->dev.of_node,

							"qcom,gcc-gfx-sdm632");

	if (compat_bin)

		gfx3d_clk_src.freq_tbl = ftbl_gfx3d_clk_src_sdm632;



	ret = of_get_fmax_vdd_class(pdev, &gcc_oxili_gfx3d_clk.c,

					"qcom,gfxfreq-corner");

	if (ret) {