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Commit 1dc1d2e9 authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'imx-fixes-rc' of git://git.pengutronix.de/git/imx/linux-2.6 into fixes 

From Sascha Hauer:

ARM i.MX fixes for v3.8-rc

This fixes a compile failure on imx_v4_v5_defconfig and a regression
introduced with enabling the MIPI clocks on i.MX51. Also one rather
cosmetic fix for the i.MX27 dts file.

* tag 'imx-fixes-rc' of git://git.pengutronix.de/git/imx/linux-2.6:
  ARM: imx: Move platform-mx2-emma to arch/arm/mach-imx/devices
  ARM i.MX51 clock: Fix regression since enabling MIPI/HSP clocks
  ARM: dts: mx27: Fix the AIPI bus for FEC
parents a93178a1 027c0a6a

arch/arm/boot/dts/imx27-3ds.dts

+4 −4
Original line number Diff line number Diff line
@@ -21,17 +21,17 @@ 
	};



	soc {

		aipi@10000000 { /* aipi */



		aipi@10000000 { /* aipi1 */

			uart1: serial@1000a000 {

				fsl,uart-has-rtscts;

				status = "okay";

			};

		};



			fec@1002b000 {

		aipi@10020000 { /* aipi2 */

			ethernet@1002b000 {

				status = "okay";

			};

		};

	};



};

arch/arm/boot/dts/imx27-phytec-phycore.dts

+7 −6
Original line number Diff line number Diff line
@@ -21,8 +21,7 @@ 
	};



	soc {

		aipi@10000000 { /* aipi */



		aipi@10000000 { /* aipi1 */

			serial@1000a000 {

				fsl,uart-has-rtscts;

				status = "okay";
@@ -38,10 +37,6 @@ 
				status = "okay";

			};



			ethernet@1002b000 {

				status = "okay";

			};



			i2c@1001d000 {

				clock-frequency = <400000>;

				status = "okay";
@@ -60,6 +55,12 @@ 
				};

			};

		};



		aipi@10020000 { /* aipi2 */

			ethernet@1002b000 {

				status = "okay";

			};

		};

	};



	nor_flash@c0000000 {

arch/arm/boot/dts/imx27.dtsi

+10 −1
Original line number Diff line number Diff line
@@ -55,7 +55,7 @@ 
			compatible = "fsl,aipi-bus", "simple-bus";

			#address-cells = <1>;

			#size-cells = <1>;

			reg = <0x10000000 0x10000000>;

			reg = <0x10000000 0x20000>;

			ranges;



			wdog: wdog@10002000 {
@@ -211,6 +211,15 @@ 
				status = "disabled";

			};



		};



		aipi@10020000 { /* AIPI2 */

			compatible = "fsl,aipi-bus", "simple-bus";

			#address-cells = <1>;

			#size-cells = <1>;

			reg = <0x10020000 0x20000>;

			ranges;



			fec: ethernet@1002b000 {

				compatible = "fsl,imx27-fec";

				reg = <0x1002b000 0x4000>;

arch/arm/mach-imx/clk-imx51-imx53.c

+16 −0
Original line number Diff line number Diff line
@@ -319,6 +319,7 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc, 
			unsigned long rate_ckih1, unsigned long rate_ckih2)

{

	int i;

	u32 val;

	struct device_node *np;



	clk[pll1_sw] = imx_clk_pllv2("pll1_sw", "osc", MX51_DPLL1_BASE);
@@ -390,6 +391,21 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc, 
	imx_print_silicon_rev("i.MX51", mx51_revision());

	clk_disable_unprepare(clk[iim_gate]);



	/*

	 * Reference Manual says: Functionality of CCDR[18] and CLPCR[23] is no

	 * longer supported. Set to one for better power saving.

	 *

	 * The effect of not setting these bits is that MIPI clocks can't be

	 * enabled without the IPU clock being enabled aswell.

	 */

	val = readl(MXC_CCM_CCDR);

	val |= 1 << 18;

	writel(val, MXC_CCM_CCDR);



	val = readl(MXC_CCM_CLPCR);

	val |= 1 << 23;

	writel(val, MXC_CCM_CLPCR);



	return 0;

}

arch/arm/plat-mxc/devices/platform-mx2-emma.c→arch/arm/mach-imx/devices/platform-mx2-emma.c

+2 −2
Original line number Diff line number Diff line
@@ -6,8 +6,8 @@ 
 * the terms of the GNU General Public License version 2 as published by the

 * Free Software Foundation.

 */

#include <mach/hardware.h>

#include <mach/devices-common.h>

#include "../hardware.h"

#include "devices-common.h"



#define imx_mx2_emmaprp_data_entry_single(soc)				\

	{								\