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Commit 1db632fb authored by Rajesh Yadav's avatar Rajesh Yadav
Browse files

drm/msm/sde: Add AHB based programming support for pcc v4 feature 



Change adds the AHB based igc v4 feature programming support to
color processing module present in CRTC.

Change-Id: I4ce494faeec1cc4aacd2d7f84f97302c5501ca42
Signed-off-by: default avatarRajesh Yadav <ryadav@codeaurora.org>
parent d490cb64

drivers/gpu/drm/msm/sde/sde_hw_color_proc_common_v4.h

+10 −0
Original line number Diff line number Diff line
@@ -55,5 +55,15 @@ enum { 
#define PCC_EN BIT(0)

#define PCC_DIS 0

#define PCC_C_OFF 0x4

#define PCC_R_OFF 0x10

#define PCC_G_OFF 0x1c

#define PCC_B_OFF 0x28

#define PCC_RG_OFF 0x34

#define PCC_RB_OFF 0x40

#define PCC_GB_OFF 0x4c

#define PCC_RGB_OFF 0x58

#define PCC_RR_OFF 0x64

#define PCC_GG_OFF 0x70

#define PCC_BB_OFF 0x7c



#endif /* _SDE_HW_COLOR_PROC_COMMON_V4_H_ */

drivers/gpu/drm/msm/sde/sde_hw_color_proc_v4.c

+75 −0
Original line number Diff line number Diff line
@@ -158,3 +158,78 @@ void sde_setup_dspp_igcv3(struct sde_hw_dspp *ctx, void *cfg) 


	SDE_REG_WRITE(&ctx->hw, IGC_OPMODE_OFF, IGC_EN);

}



void sde_setup_dspp_pccv4(struct sde_hw_dspp *ctx, void *cfg)

{

	struct sde_hw_cp_cfg *hw_cfg = cfg;

	struct drm_msm_pcc *pcc_cfg;

	struct drm_msm_pcc_coeff *coeffs = NULL;

	int i = 0;

	u32 base = 0;



	if (!ctx || !cfg) {

		DRM_ERROR("invalid param ctx %pK cfg %pK\n", ctx, cfg);

		return;

	}



	if (!hw_cfg->payload) {

		DRM_DEBUG_DRIVER("disable pcc feature\n");

		SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->pcc.base, 0);

		return;

	}



	if (hw_cfg->len != sizeof(struct drm_msm_pcc)) {

		DRM_ERROR("invalid size of payload len %d exp %zd\n",

				hw_cfg->len, sizeof(struct drm_msm_pcc));

		return;

	}



	pcc_cfg = hw_cfg->payload;



	for (i = 0; i < PCC_NUM_PLANES; i++) {

		base = ctx->cap->sblk->pcc.base + (i * sizeof(u32));

		switch (i) {

		case 0:

			coeffs = &pcc_cfg->r;

			SDE_REG_WRITE(&ctx->hw,

				base + PCC_RR_OFF, pcc_cfg->r_rr);

			SDE_REG_WRITE(&ctx->hw,

				base + PCC_GG_OFF, pcc_cfg->r_gg);

			SDE_REG_WRITE(&ctx->hw,

				base + PCC_BB_OFF, pcc_cfg->r_bb);

			break;

		case 1:

			coeffs = &pcc_cfg->g;

			SDE_REG_WRITE(&ctx->hw,

				base + PCC_RR_OFF, pcc_cfg->g_rr);

			SDE_REG_WRITE(&ctx->hw,

				base + PCC_GG_OFF, pcc_cfg->g_gg);

			SDE_REG_WRITE(&ctx->hw,

				base + PCC_BB_OFF, pcc_cfg->g_bb);

			break;

		case 2:

			coeffs = &pcc_cfg->b;

			SDE_REG_WRITE(&ctx->hw,

				base + PCC_RR_OFF, pcc_cfg->b_rr);

			SDE_REG_WRITE(&ctx->hw,

				base + PCC_GG_OFF, pcc_cfg->b_gg);

			SDE_REG_WRITE(&ctx->hw,

				base + PCC_BB_OFF, pcc_cfg->b_bb);

			break;

		default:

			DRM_ERROR("invalid pcc plane: %d\n", i);

			return;

		}



		SDE_REG_WRITE(&ctx->hw, base + PCC_C_OFF, coeffs->c);

		SDE_REG_WRITE(&ctx->hw, base + PCC_R_OFF, coeffs->r);

		SDE_REG_WRITE(&ctx->hw, base + PCC_G_OFF, coeffs->g);

		SDE_REG_WRITE(&ctx->hw, base + PCC_B_OFF, coeffs->b);

		SDE_REG_WRITE(&ctx->hw, base + PCC_RG_OFF, coeffs->rg);

		SDE_REG_WRITE(&ctx->hw, base + PCC_RB_OFF, coeffs->rb);

		SDE_REG_WRITE(&ctx->hw, base + PCC_GB_OFF, coeffs->gb);

		SDE_REG_WRITE(&ctx->hw, base + PCC_RGB_OFF, coeffs->rgb);

	}



	SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->pcc.base, PCC_EN);

}

drivers/gpu/drm/msm/sde/sde_hw_color_proc_v4.h

+7 −0
Original line number Diff line number Diff line
@@ -29,5 +29,12 @@ void sde_setup_dspp_3d_gamutv4(struct sde_hw_dspp *ctx, void *cfg); 
 * @cfg: pointer to sde_hw_cp_cfg

 */

void sde_setup_dspp_igcv3(struct sde_hw_dspp *ctx, void *cfg);

/**

 * sde_setup_dspp_pccv4 - Function for pcc v4 version feature

 *                             programming.

 * @ctx: dspp ctx pointer

 * @cfg: pointer to sde_hw_cp_cfg

 */

void sde_setup_dspp_pccv4(struct sde_hw_dspp *ctx, void *cfg);



#endif /* _SDE_HW_COLOR_PROC_V4_H_ */

drivers/gpu/drm/msm/sde/sde_hw_dspp.c

+2 −1
Original line number Diff line number Diff line
@@ -65,7 +65,8 @@ static void _setup_dspp_ops(struct sde_hw_dspp *c, unsigned long features) 
					c->ops.setup_pcc =

						reg_dmav1_setup_dspp_pccv4;

				else

					c->ops.setup_pcc = NULL;

					c->ops.setup_pcc =

						sde_setup_dspp_pccv4;

			}

			break;

		case SDE_DSPP_HSIC: