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Commit 1db0dffe authored by Satyajit Desai's avatar Satyajit Desai Committed by Gerrit - the friendly Code Review server
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ARM: dts: msm: Probe coresight devices using amba framework on SDM845 



Add device tree changes to probe TPDMs, TPDAs, CTIs and
replicators using the amba bus framework for SDM845.

Change-Id: I077f4158b329a95ba6cccbc444841aa13f69565d
Signed-off-by: default avatarSatyajit Desai <sadesai@codeaurora.org>
parent 045b56b0

arch/arm64/boot/dts/qcom/sdm845-coresight.dtsi

+157 −95
Original line number Diff line number Diff line
@@ -167,7 +167,8 @@ 
	};



	tpda_swao: tpda@6b01000 {

		compatible = "qcom,coresight-tpda";

		compatible = "arm,primecell";

		arm,primecell-periphid = <0x0003b969>;

		reg = <0x6b01000 0x1000>;

		reg-names = "tpda-base";
@@ -178,7 +179,7 @@ 
		qcom,cmb-elem-size = <0 64>;



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "core_clk";

		clock-names = "apb_pclk";



		ports {

			#address-cells = <1>;
@@ -215,7 +216,8 @@ 
	};



	tpdm_swao0: tpdm@6b02000 {

		compatible = "qcom,coresight-tpdm";

		compatible = "arm,primecell";

		arm,primecell-periphid = <0x0003b968>;



		reg = <0x6b02000 0x1000>;

		reg-names = "tpdm-base";
@@ -223,7 +225,7 @@ 
		coresight-name = "coresight-tpdm-swao-0";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "core_clk";

		clock-names = "apb_pclk";



		port {

			tpdm_swao0_out_tpda_swao: endpoint {
@@ -233,14 +235,15 @@ 
	};



	tpdm_swao1: tpdm@6b03000 {

		compatible = "qcom,coresight-tpdm";

		compatible = "arm,primecell";

		arm,primecell-periphid = <0x0003b968>;

		reg = <0x6b03000 0x1000>;

		reg-names = "tpdm-base";



		coresight-name="coresight-tpdm-swao-1";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "core_clk";

		clock-names = "apb_pclk";



		port {

			tpdm_swao1_out_tpda_swao: endpoint {
@@ -485,7 +488,8 @@ 
	};



	tpda: tpda@6004000 {

		compatible = "qcom,coresight-tpda";

		compatible = "arm,primecell";

		arm,primecell-periphid = <0x0003b969>;

		reg = <0x6004000 0x1000>;

		reg-names = "tpda-base";
@@ -507,7 +511,7 @@ 
				     <13 64>;



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "core_clk";

		clock-names = "apb_pclk";



		ports {

			#address-cells = <1>;
@@ -631,7 +635,8 @@ 
	};



	tpda_modem: tpda@6831000 {

		compatible = "qcom,coresight-tpda";

		compatible = "arm,primecell";

		arm,primecell-periphid = <0x0003b969>;

		reg = <0x6831000 0x1000>;

		reg-names = "tpda-base";
@@ -642,7 +647,7 @@ 
		qcom,cmb-elem-size = <0 64>;



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "core_clk";

		clock-names = "apb_pclk";



		ports {

			#address-cells = <1>;
@@ -667,14 +672,15 @@ 
	};



	tpdm_modem: tpdm@6830000 {

		compatible = "qcom,coresight-tpdm";

		compatible = "arm,primecell";

		arm,primecell-periphid = <0x0003b968>;

		reg = <0x6830000 0x1000>;

		reg-names = "tpdm-base";



		coresight-name = "coresight-tpdm-modem";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "core_clk";

		clock-names = "apb_pclk";



		port {

			tpdm_modem_out_tpda_modem: endpoint {
@@ -736,14 +742,15 @@ 
	};



	tpdm_center: tpdm@6c28000 {

		compatible = "qcom,coresight-tpdm";

		compatible = "arm,primecell";

		arm,primecell-periphid = <0x0003b968>;

		reg = <0x6c28000 0x1000>;

		reg-names = "tpdm-base";



		coresight-name = "coresight-tpdm-center";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "core_clk";

		clock-names = "apb_pclk";



		port {

			tpdm_center_out_tpda: endpoint {
@@ -753,14 +760,15 @@ 
	};



	tpdm_north: tpdm@6a24000 {

		compatible = "qcom,coresight-tpdm";

		compatible = "arm,primecell";

		arm,primecell-periphid = <0x0003b968>;

		reg = <0x6a24000 0x1000>;

		reg-names = "tpdm-base";



		coresight-name = "coresight-tpdm-north";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "core_clk";

		clock-names = "apb_pclk";



		port {

			tpdm_north_out_tpda: endpoint {
@@ -770,14 +778,15 @@ 
	};



	tpdm_qm: tpdm@69d0000 {

		compatible = "qcom,coresight-tpdm";

		compatible = "arm,primecell";

		arm,primecell-periphid = <0x0003b968>;

		reg = <0x69d0000 0x1000>;

		reg-names = "tpdm-base";



		coresight-name = "coresight-tpdm-qm";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "core_clk";

		clock-names = "apb_pclk";



		port {

			tpdm_qm_out_tpda: endpoint {
@@ -787,7 +796,8 @@ 
	};



	tpda_apss: tpda@7862000 {

		compatible = "qcom,coresight-tpda";

		compatible = "arm,primecell";

		arm,primecell-periphid = <0x0003b969>;

		reg = <0x7862000 0x1000>;

		reg-names = "tpda-base";
@@ -797,7 +807,7 @@ 
		qcom,dsb-elem-size = <0 32>;



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "core_clk";

		clock-names = "apb_pclk";



		ports {

			#address-cells = <1>;
@@ -822,14 +832,15 @@ 
	};



	tpdm_apss: tpdm@7860000 {

		compatible = "qcom,coresight-tpdm";

		compatible = "arm,primecell";

		arm,primecell-periphid = <0x0003b968>;

		reg = <0x7860000 0x1000>;

		reg-names = "tpdm-base";



		coresight-name = "coresight-tpdm-apss";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "core_clk";

		clock-names = "apb_pclk";



		port {

			tpdm_apss_out_tpda_apss: endpoint {
@@ -839,7 +850,8 @@ 
	};



	tpda_llm_silver: tpda@78c0000 {

		compatible = "qcom,coresight-tpda";

		compatible = "arm,primecell";

		arm,primecell-periphid = <0x0003b969>;

		reg = <0x78c0000 0x1000>;

		reg-names = "tpda-base";
@@ -849,7 +861,7 @@ 
		qcom,cmb-elem-size = <0 64>;



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "core_clk";

		clock-names = "apb_pclk";



		ports {

			#address-cells = <1>;
@@ -874,14 +886,15 @@ 
	};



	tpdm_llm_silver: tpdm@78a0000 {

		compatible = "qcom,coresight-tpdm";

		compatible = "arm,primecell";

		arm,primecell-periphid = <0x0003b968>;

		reg = <0x78a0000 0x1000>;

		reg-names = "tpdm-base";



		coresight-name = "coresight-tpdm-llm-silver";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "core_clk";

		clock-names = "apb_pclk";



		port {

			tpdm_llm_silver_out_tpda_llm_silver: endpoint {
@@ -892,7 +905,8 @@ 
	};



	tpda_llm_gold: tpda@78d0000 {

		compatible = "qcom,coresight-tpda";

		compatible = "arm,primecell";

		arm,primecell-periphid = <0x0003b969>;

		reg = <0x78d0000 0x1000>;

		reg-names = "tpda-base";
@@ -902,7 +916,7 @@ 
		qcom,cmb-elem-size = <0 64>;



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "core_clk";

		clock-names = "apb_pclk";



		ports {

			#address-cells = <1>;
@@ -927,14 +941,15 @@ 
	};



	tpdm_llm_gold: tpdm@78b0000 {

		compatible = "qcom,coresight-tpdm";

		compatible = "arm,primecell";

		arm,primecell-periphid = <0x0003b968>;

		reg = <0x78b0000 0x1000>;

		reg-names = "tpdm-base";



		coresight-name = "coresight-tpdm-llm-gold";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "core_clk";

		clock-names = "apb_pclk";



		port {

			tpdm_llm_gold_out_tpda_llm_gold: endpoint {
@@ -980,14 +995,15 @@ 
	};



	tpdm_mm: tpdm@6c08000 {

		compatible = "qcom,coresight-tpdm";

		compatible = "arm,primecell";

		arm,primecell-periphid = <0x0003b968>;

		reg = <0x6c08000 0x1000>;

		reg-names = "tpdm-base";



		coresight-name = "coresight-tpdm-mm";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "core_clk";

		clock-names = "apb_pclk";



		port {

			tpdm_mm_out_funnel_dl_mm: endpoint {
@@ -1032,14 +1048,15 @@ 
	};



	tpdm_ddr: tpdm@69e0000 {

		compatible = "qcom,coresight-tpdm";

		compatible = "arm,primecell";

		arm,primecell-periphid = <0x0003b968>;

		reg = <0x69e0000 0x1000>;

		reg-names = "tpdm-base";



		coresight-name = "coresight-tpdm-ddr";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "core_clk";

		clock-names = "apb_pclk";



		port {

			tpdm_ddr_out_funnel_ddr_0: endpoint {
@@ -1049,14 +1066,15 @@ 
	};



	tpdm_pimem: tpdm@6850000 {

		compatible = "qcom,coresight-tpdm";

		compatible = "arm,primecell";

		arm,primecell-periphid = <0x0003b968>;

		reg = <0x6850000 0x1000>;

		reg-names = "tpdm-base";



		coresight-name = "coresight-tpdm-pimem";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "core_clk";

		clock-names = "apb_pclk";



		port {

			tpdm_pimem_out_tpda: endpoint {
@@ -1066,14 +1084,15 @@ 
	};



	tpdm_vsense: tpdm@6840000 {

		compatible = "qcom,coresight-tpdm";

		compatible = "arm,primecell";

		arm,primecell-periphid = <0x0003b968>;

		reg = <0x6840000 0x1000>;

		reg-names = "tpdm-base";



		coresight-name = "coresight-tpdm-vsense";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "core_clk";

		clock-names = "apb_pclk";



		port{

			tpdm_vsense_out_tpda: endpoint {
@@ -1083,7 +1102,8 @@ 
	};



	tpda_olc: tpda@7832000 {

		compatible = "qcom,coresight-tpda";

		compatible = "arm,primecell";

		arm,primecell-periphid = <0x0003b969>;

		reg = <0x7832000 0x1000>;

		reg-names = "tpda-base";
@@ -1093,7 +1113,7 @@ 
		qcom,cmb-elem-size = <0 64>;



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "core_clk";

		clock-names = "apb_pclk";



		ports {

			#address-cells = <1>;
@@ -1117,14 +1137,15 @@ 
	};



	tpdm_olc: tpdm@7830000 {

		compatible = "qcom,coresight-tpdm";

		compatible = "arm,primecell";

		arm,primecell-periphid = <0x0003b968>;

		reg = <0x7830000 0x1000>;

		reg-names = "tpdm-base";



		coresight-name = "coresight-tpdm-olc";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "core_clk";

		clock-names = "apb_pclk";



		port{

			tpdm_olc_out_tpda_olc: endpoint {
@@ -1134,7 +1155,8 @@ 
	};



	tpda_spss: tpda@6882000 {

		compatible = "qcom,coresight-tpda";

		compatible = "arm,primecell";

		arm,primecell-periphid = <0x0003b969>;

		reg = <0x6882000 0x1000>;

		reg-names = "tpda-base";
@@ -1144,7 +1166,7 @@ 
		qcom,dsb-elem-size = <0 32>;



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "core_clk";

		clock-names = "apb_pclk";



		ports {

			#address-cells = <1>;
@@ -1168,15 +1190,15 @@ 
	};



	tpdm_spss: tpdm@6880000 {

		compatible = "qcom,coresight-tpdm";

		compatible = "arm,primecell";

		arm,primecell-periphid = <0x0003b968>;

		reg = <0x6880000 0x1000>;

		reg-names = "tpdm-base";



		coresight-name = "coresight-tpdm-spss";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "core_clk";



		clock-names = "apb_pclk";

		qcom,msr-fix-req;



		port{
@@ -1257,183 +1279,215 @@ 
	};



	cti0: cti@6010000 {

		compatible = "arm,coresight-cti";

		compatible = "arm,primecell";

		arm,primecell-periphid = <0x0003b966>;

		reg = <0x6010000 0x1000>;

		reg-names = "cti-base";



		coresight-name = "coresight-cti0";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "core_clk";

		clock-names = "apb_pclk";



	};



	cti1: cti@6011000 {

		compatible = "arm,coresight-cti";

		compatible = "arm,primecell";

		arm,primecell-periphid = <0x0003b966>;

		reg = <0x6011000 0x1000>;

		reg-names = "cti-base";



		coresight-name = "coresight-cti1";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "core_clk";

		clock-names = "apb_pclk";



	};



	cti2: cti@6012000 {

		compatible = "arm,coresight-cti";

		compatible = "arm,primecell";

		arm,primecell-periphid = <0x0003b966>;

		reg = <0x6012000 0x1000>;

		reg-names = "cti-base";



		coresight-name = "coresight-cti2";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "core_clk";

		clock-names = "apb_pclk";

	};



	cti3: cti@6013000 {

		compatible = "arm,coresight-cti";

		compatible = "arm,primecell";

		arm,primecell-periphid = <0x0003b966>;

		reg = <0x6013000 0x1000>;

		reg-names = "cti-base";



		coresight-name = "coresight-cti3";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "core_clk";

		clock-names = "apb_pclk";



	};



	cti4: cti@6014000 {

		compatible = "arm,coresight-cti";

		compatible = "arm,primecell";

		arm,primecell-periphid = <0x0003b966>;

		reg = <0x6014000 0x1000>;

		reg-names = "cti-base";



		coresight-name = "coresight-cti4";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "core_clk";

		clock-names = "apb_pclk";



	};



	cti5: cti@6015000 {

		compatible = "arm,coresight-cti";

		compatible = "arm,primecell";

		arm,primecell-periphid = <0x0003b966>;

		reg = <0x6015000 0x1000>;

		reg-names = "cti-base";



		coresight-name = "coresight-cti5";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "core_clk";

		clock-names = "apb_pclk";



	};



	cti6: cti@6016000 {

		compatible = "arm,coresight-cti";

		compatible = "arm,primecell";

		arm,primecell-periphid = <0x0003b966>;

		reg = <0x6016000 0x1000>;

		reg-names = "cti-base";



		coresight-name = "coresight-cti6";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "core_clk";

		clock-names = "apb_pclk";



	};



	cti7: cti@6017000 {

		compatible = "arm,coresight-cti";

		compatible = "arm,primecell";

		arm,primecell-periphid = <0x0003b966>;

		reg = <0x6017000 0x1000>;

		reg-names = "cti-base";



		coresight-name = "coresight-cti7";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "core_clk";

		clock-names = "apb_pclk";



	};



	cti8: cti@6018000 {

		compatible = "arm,coresight-cti";

		compatible = "arm,primecell";

		arm,primecell-periphid = <0x0003b966>;

		reg = <0x6018000 0x1000>;

		reg-names = "cti-base";



		coresight-name = "coresight-cti8";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "core_clk";

		clock-names = "apb_pclk";



	};



	cti9: cti@6019000 {

		compatible = "arm,coresight-cti";

		compatible = "arm,primecell";

		arm,primecell-periphid = <0x0003b966>;

		reg = <0x6019000 0x1000>;

		reg-names = "cti-base";



		coresight-name = "coresight-cti9";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "core_clk";

		clock-names = "apb_pclk";



	};



	cti10: cti@601a000 {

		compatible = "arm,coresight-cti";

		compatible = "arm,primecell";

		arm,primecell-periphid = <0x0003b966>;

		reg = <0x601a000 0x1000>;

		reg-names = "cti-base";



		coresight-name = "coresight-cti10";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "core_clk";

		clock-names = "apb_pclk";



	};



	cti11: cti@601b000 {

		compatible = "arm,coresight-cti";

		compatible = "arm,primecell";

		arm,primecell-periphid = <0x0003b966>;

		reg = <0x601b000 0x1000>;

		reg-names = "cti-base";



		coresight-name = "coresight-cti11";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "core_clk";

		clock-names = "apb_pclk";



	};



	cti12: cti@601c000 {

		compatible = "arm,coresight-cti";

		compatible = "arm,primecell";

		arm,primecell-periphid = <0x0003b966>;

		reg = <0x601c000 0x1000>;

		reg-names = "cti-base";



		coresight-name = "coresight-cti12";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "core_clk";

		clock-names = "apb_pclk";



	};



	cti13: cti@601d000 {

		compatible = "arm,coresight-cti";

		compatible = "arm,primecell";

		arm,primecell-periphid = <0x0003b966>;

		reg = <0x601d000 0x1000>;

		reg-names = "cti-base";



		coresight-name = "coresight-cti13";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "core_clk";

		clock-names = "apb_pclk";



	};



	cti14: cti@601e000 {

		compatible = "arm,coresight-cti";

		compatible = "arm,primecell";

		arm,primecell-periphid = <0x0003b966>;

		reg = <0x601e000 0x1000>;

		reg-names = "cti-base";



		coresight-name = "coresight-cti14";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "core_clk";

		clock-names = "apb_pclk";



	};



	cti15: cti@601f000 {

		compatible = "arm,coresight-cti";

		compatible = "arm,primecell";

		arm,primecell-periphid = <0x0003b966>;

		reg = <0x601f000 0x1000>;

		reg-names = "cti-base";



		coresight-name = "coresight-cti15";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "core_clk";

		clock-names = "apb_pclk";



	};



	cti_cpu0: cti@7020000 {

		compatible = "arm,coresight-cti";

		compatible = "arm,primecell";

		arm,primecell-periphid = <0x0003b966>;

		reg = <0x7020000 0x1000>;

		reg-names = "cti-base";
@@ -1441,11 +1495,13 @@ 
		cpu = <&CPU0>;



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "core_clk";

		clock-names = "apb_pclk";



	};



	cti_cpu1: cti@7120000 {

		compatible = "arm,coresight-cti";

		compatible = "arm,primecell";

		arm,primecell-periphid = <0x0003b966>;

		reg = <0x7120000 0x1000>;

		reg-names = "cti-base";
@@ -1453,11 +1509,12 @@ 
		cpu = <&CPU1>;



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "core_clk";

		clock-names = "apb_pclk";

	};



	cti_cpu2: cti@7220000 {

		compatible = "arm,coresight-cti";

		compatible = "arm,primecell";

		arm,primecell-periphid = <0x0003b966>;

		reg = <0x7220000 0x1000>;

		reg-names = "cti-base";
@@ -1465,11 +1522,12 @@ 
		cpu = <&CPU2>;



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "core_clk";

		clock-names = "apb_pclk";

	};



	cti_cpu3: cti@7320000 {

		compatible = "arm,coresight-cti";

		compatible = "arm,primecell";

		arm,primecell-periphid = <0x0003b966>;

		reg = <0x7320000 0x1000>;

		reg-names = "cti-base";
@@ -1477,11 +1535,12 @@ 
		cpu = <&CPU3>;



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "core_clk";

		clock-names = "apb_pclk";

	};



	cti_cpu4: cti@7420000 {

		compatible = "arm,coresight-cti";

		compatible = "arm,primecell";

		arm,primecell-periphid = <0x0003b966>;

		reg = <0x7420000 0x1000>;

		reg-names = "cti-base";
@@ -1489,11 +1548,12 @@ 
		cpu = <&CPU4>;



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "core_clk";

		clock-names = "apb_pclk";

	};



	cti_cpu5: cti@7520000 {

		compatible = "arm,coresight-cti";

		compatible = "arm,primecell";

		arm,primecell-periphid = <0x0003b966>;

		reg = <0x7520000 0x1000>;

		reg-names = "cti-base";
@@ -1501,11 +1561,12 @@ 
		cpu = <&CPU5>;



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "core_clk";

		clock-names = "apb_pclk";

	};



	cti_cpu6: cti@7620000 {

		compatible = "arm,coresight-cti";

		compatible = "arm,primecell";

		arm,primecell-periphid = <0x0003b966>;

		reg = <0x7620000 0x1000>;

		reg-names = "cti-base";
@@ -1513,11 +1574,12 @@ 
		cpu = <&CPU6>;



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "core_clk";

		clock-names = "apb_pclk";

	};



	cti_cpu7: cti@7720000 {

		compatible = "arm,coresight-cti";

		compatible = "arm,primecell";

		arm,primecell-periphid = <0x0003b966>;

		reg = <0x7720000 0x1000>;

		reg-names = "cti-base";
@@ -1525,7 +1587,7 @@ 
		cpu = <&CPU7>;



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "core_clk";

		clock-names = "apb_pclk";

	};



	dummy_eud: dummy_sink {