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Commit 1c44f5f1 authored by Philipp Zabel's avatar Philipp Zabel Committed by Linus Torvalds
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gpiolib support for the PXA architecture 



This adds gpiolib support for the PXA architecture:
  - move all GPIO API functions from generic.c into gpio.c
  - convert the gpio_get/set_value macros into inline functions

This makes it easier to hook up GPIOs provided by external chips like
ASICs and CPLDs.

Signed-off-by: default avatarPhilipp Zabel <philipp.zabel@gmail.com>
Signed-off-by: default avatarDavid Brownell <dbrownell@users.sourceforge.net>
Acked-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
Cc: Jean Delvare <khali@linux-fr.org>
Cc: Eric Miao <eric.miao@marvell.com>
Cc: Sam Ravnborg <sam@ravnborg.org>
Cc: Haavard Skinnemoen <hskinnemoen@atmel.com>
Cc: Ben Gardner <bgardner@wabtec.com>
Signed-off-by: default avatarAndrew Morton <akpm@linux-foundation.org>
[ Minor ARM fixup from David Brownell folded into this ]
Signed-off-by: default avatarLinus Torvalds <torvalds@linux-foundation.org>
parent 7c2db759

arch/arm/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -385,6 +385,7 @@ config ARCH_PXA 
	depends on MMU

	select ARCH_MTD_XIP

	select GENERIC_GPIO

	select HAVE_GPIO_LIB

	select GENERIC_TIME

	select GENERIC_CLOCKEVENTS

	select TICK_ONESHOT

arch/arm/mach-pxa/Makefile

+2 −1
Original line number Diff line number Diff line
@@ -3,7 +3,8 @@ 
#



# Common support (must be linked before board specific support)

obj-y				+= clock.o devices.o generic.o irq.o dma.o time.o

obj-y				+= clock.o devices.o generic.o irq.o dma.o \

				   time.o gpio.o

obj-$(CONFIG_PXA25x)		+= pxa25x.o

obj-$(CONFIG_PXA27x)		+= pxa27x.o

obj-$(CONFIG_PXA3xx)		+= pxa3xx.o mfp.o smemc.o

arch/arm/mach-pxa/generic.c

+0 −93
Original line number Diff line number Diff line
@@ -32,7 +32,6 @@ 
#include <asm/mach/map.h>



#include <asm/arch/pxa-regs.h>

#include <asm/arch/gpio.h>



#include "generic.h"
@@ -66,97 +65,6 @@ unsigned int get_memclk_frequency_10khz(void) 
}

EXPORT_SYMBOL(get_memclk_frequency_10khz);



/*

 * Handy function to set GPIO alternate functions

 */

int pxa_last_gpio;



int pxa_gpio_mode(int gpio_mode)

{

	unsigned long flags;

	int gpio = gpio_mode & GPIO_MD_MASK_NR;

	int fn = (gpio_mode & GPIO_MD_MASK_FN) >> 8;

	int gafr;



	if (gpio > pxa_last_gpio)

		return -EINVAL;



	local_irq_save(flags);

	if (gpio_mode & GPIO_DFLT_LOW)

		GPCR(gpio) = GPIO_bit(gpio);

	else if (gpio_mode & GPIO_DFLT_HIGH)

		GPSR(gpio) = GPIO_bit(gpio);

	if (gpio_mode & GPIO_MD_MASK_DIR)

		GPDR(gpio) |= GPIO_bit(gpio);

	else

		GPDR(gpio) &= ~GPIO_bit(gpio);

	gafr = GAFR(gpio) & ~(0x3 << (((gpio) & 0xf)*2));

	GAFR(gpio) = gafr |  (fn  << (((gpio) & 0xf)*2));

	local_irq_restore(flags);



	return 0;

}



EXPORT_SYMBOL(pxa_gpio_mode);



int gpio_direction_input(unsigned gpio)

{

	unsigned long flags;

	u32 mask;



	if (gpio > pxa_last_gpio)

		return -EINVAL;



	mask = GPIO_bit(gpio);

	local_irq_save(flags);

	GPDR(gpio) &= ~mask;

	local_irq_restore(flags);



	return 0;

}

EXPORT_SYMBOL(gpio_direction_input);



int gpio_direction_output(unsigned gpio, int value)

{

	unsigned long flags;

	u32 mask;



	if (gpio > pxa_last_gpio)

		return -EINVAL;



	mask = GPIO_bit(gpio);

	local_irq_save(flags);

	if (value)

		GPSR(gpio) = mask;

	else

		GPCR(gpio) = mask;

	GPDR(gpio) |= mask;

	local_irq_restore(flags);



	return 0;

}

EXPORT_SYMBOL(gpio_direction_output);



/*

 * Return GPIO level

 */

int pxa_gpio_get_value(unsigned gpio)

{

	return __gpio_get_value(gpio);

}



EXPORT_SYMBOL(pxa_gpio_get_value);



/*

 * Set output GPIO level

 */

void pxa_gpio_set_value(unsigned gpio, int value)

{

	__gpio_set_value(gpio, value);

}



EXPORT_SYMBOL(pxa_gpio_set_value);



/*

 * Routine to safely enable or disable a clock in the CKEN

 */
@@ -172,7 +80,6 @@ void __pxa_set_cken(int clock, int enable) 


	local_irq_restore(flags);

}



EXPORT_SYMBOL(__pxa_set_cken);



/*

arch/arm/mach-pxa/generic.h

+1 −0
Original line number Diff line number Diff line
@@ -16,6 +16,7 @@ extern void __init pxa_init_irq_low(void); 
extern void __init pxa_init_irq_high(void);

extern void __init pxa_init_irq_gpio(int gpio_nr);

extern void __init pxa_init_irq_set_wake(int (*set_wake)(unsigned int, unsigned int));

extern void __init pxa_init_gpio(int gpio_nr);

extern void __init pxa25x_init_irq(void);

extern void __init pxa27x_init_irq(void);

extern void __init pxa3xx_init_irq(void);

arch/arm/mach-pxa/gpio.c

0 → 100644
+197 −0
Original line number Diff line number Diff line 
/*

 *  linux/arch/arm/mach-pxa/gpio.c

 *

 *  Generic PXA GPIO handling

 *

 *  Author:	Nicolas Pitre

 *  Created:	Jun 15, 2001

 *  Copyright:	MontaVista Software Inc.

 *

 *  This program is free software; you can redistribute it and/or modify

 *  it under the terms of the GNU General Public License version 2 as

 *  published by the Free Software Foundation.

 */



#include <linux/init.h>

#include <linux/module.h>



#include <asm/gpio.h>

#include <asm/hardware.h>

#include <asm/io.h>

#include <asm/arch/pxa-regs.h>



#include "generic.h"





struct pxa_gpio_chip {

	struct gpio_chip chip;

	void __iomem     *regbase;

};



int pxa_last_gpio;



/*

 * Configure pins for GPIO or other functions

 */

int pxa_gpio_mode(int gpio_mode)

{

	unsigned long flags;

	int gpio = gpio_mode & GPIO_MD_MASK_NR;

	int fn = (gpio_mode & GPIO_MD_MASK_FN) >> 8;

	int gafr;



	if (gpio > pxa_last_gpio)

		return -EINVAL;



	local_irq_save(flags);

	if (gpio_mode & GPIO_DFLT_LOW)

		GPCR(gpio) = GPIO_bit(gpio);

	else if (gpio_mode & GPIO_DFLT_HIGH)

		GPSR(gpio) = GPIO_bit(gpio);

	if (gpio_mode & GPIO_MD_MASK_DIR)

		GPDR(gpio) |= GPIO_bit(gpio);

	else

		GPDR(gpio) &= ~GPIO_bit(gpio);

	gafr = GAFR(gpio) & ~(0x3 << (((gpio) & 0xf)*2));

	GAFR(gpio) = gafr |  (fn  << (((gpio) & 0xf)*2));

	local_irq_restore(flags);



	return 0;

}

EXPORT_SYMBOL(pxa_gpio_mode);



static int pxa_gpio_direction_input(struct gpio_chip *chip, unsigned offset)

{

	unsigned long        flags;

	u32                  mask = 1 << offset;

	u32                  value;

	struct pxa_gpio_chip *pxa;

	void __iomem         *gpdr;



	pxa = container_of(chip, struct pxa_gpio_chip, chip);

	gpdr = pxa->regbase + GPDR_OFFSET;

	local_irq_save(flags);

	value = __raw_readl(gpdr);

	value &= ~mask;

	__raw_writel(value, gpdr);

	local_irq_restore(flags);



	return 0;

}



static int pxa_gpio_direction_output(struct gpio_chip *chip,

					unsigned offset, int value)

{

	unsigned long        flags;

	u32                  mask = 1 << offset;

	u32                  tmp;

	struct pxa_gpio_chip *pxa;

	void __iomem         *gpdr;



	pxa = container_of(chip, struct pxa_gpio_chip, chip);

	__raw_writel(mask,

			pxa->regbase + (value ? GPSR_OFFSET : GPCR_OFFSET));

	gpdr = pxa->regbase + GPDR_OFFSET;

	local_irq_save(flags);

	tmp = __raw_readl(gpdr);

	tmp |= mask;

	__raw_writel(tmp, gpdr);

	local_irq_restore(flags);



	return 0;

}



/*

 * Return GPIO level

 */

static int pxa_gpio_get(struct gpio_chip *chip, unsigned offset)

{

	u32                  mask = 1 << offset;

	struct pxa_gpio_chip *pxa;



	pxa = container_of(chip, struct pxa_gpio_chip, chip);

	return __raw_readl(pxa->regbase + GPLR_OFFSET) & mask;

}



/*

 * Set output GPIO level

 */

static void pxa_gpio_set(struct gpio_chip *chip, unsigned offset, int value)

{

	u32                  mask = 1 << offset;

	struct pxa_gpio_chip *pxa;



	pxa = container_of(chip, struct pxa_gpio_chip, chip);



	if (value)

		__raw_writel(mask, pxa->regbase + GPSR_OFFSET);

	else

		__raw_writel(mask, pxa->regbase + GPCR_OFFSET);

}



static struct pxa_gpio_chip pxa_gpio_chip[] = {

	[0] = {

		.regbase = GPIO0_BASE,

		.chip = {

			.label            = "gpio-0",

			.direction_input  = pxa_gpio_direction_input,

			.direction_output = pxa_gpio_direction_output,

			.get              = pxa_gpio_get,

			.set              = pxa_gpio_set,

			.base             = 0,

			.ngpio            = 32,

		},

	},

	[1] = {

		.regbase = GPIO1_BASE,

		.chip = {

			.label            = "gpio-1",

			.direction_input  = pxa_gpio_direction_input,

			.direction_output = pxa_gpio_direction_output,

			.get              = pxa_gpio_get,

			.set              = pxa_gpio_set,

			.base             = 32,

			.ngpio            = 32,

		},

	},

	[2] = {

		.regbase = GPIO2_BASE,

		.chip = {

			.label            = "gpio-2",

			.direction_input  = pxa_gpio_direction_input,

			.direction_output = pxa_gpio_direction_output,

			.get              = pxa_gpio_get,

			.set              = pxa_gpio_set,

			.base             = 64,

			.ngpio            = 32, /* 21 for PXA25x */

		},

	},

#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)

	[3] = {

		.regbase = GPIO3_BASE,

		.chip = {

			.label            = "gpio-3",

			.direction_input  = pxa_gpio_direction_input,

			.direction_output = pxa_gpio_direction_output,

			.get              = pxa_gpio_get,

			.set              = pxa_gpio_set,

			.base             = 96,

			.ngpio            = 32,

		},

	},

#endif

};



void __init pxa_init_gpio(int gpio_nr)

{

	int i;



	/* add a GPIO chip for each register bank.

	 * the last PXA25x register only contains 21 GPIOs

	 */

	for (i = 0; i < gpio_nr; i += 32) {

		if (i+32 > gpio_nr)

			pxa_gpio_chip[i/32].chip.ngpio = gpio_nr - i;

		gpiochip_add(&pxa_gpio_chip[i/32].chip);

	}

}