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Commit 1c0035d7 authored by Shawn Guo's avatar Shawn Guo Committed by Mike Turquette
Browse files

clk: pass parent_rate into .set_rate 



For most of .set_rate implementation, parent_rate will be used, so just
like passing parent_rate into .recalc_rate, let's pass parent_rate into
.set_rate too.

It also updates the kernel doc for .set_rate ops.

Signed-off-by: default avatarShawn Guo <shawn.guo@linaro.org>
Signed-off-by: default avatarMike Turquette <mturquette@linaro.org>
parent 81536e07

drivers/clk/clk-divider.c

+3 −2
Original line number Diff line number Diff line
@@ -111,14 +111,15 @@ static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate, 
	return *prate / div;

}



static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate)

static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,

				unsigned long parent_rate)

{

	struct clk_divider *divider = to_clk_divider(hw);

	unsigned int div;

	unsigned long flags = 0;

	u32 val;



	div = __clk_get_rate(__clk_get_parent(hw->clk)) / rate;

	div = parent_rate / rate;



	if (!(divider->flags & CLK_DIVIDER_ONE_BASED))

		div--;

drivers/clk/clk.c

+1 −1
Original line number Diff line number Diff line
@@ -848,7 +848,7 @@ static void clk_change_rate(struct clk *clk) 
	old_rate = clk->rate;



	if (clk->ops->set_rate)

		clk->ops->set_rate(clk->hw, clk->new_rate);

		clk->ops->set_rate(clk->hw, clk->new_rate, clk->parent->rate);



	if (clk->ops->recalc_rate)

		clk->rate = clk->ops->recalc_rate(clk->hw,

include/linux/clk-provider.h

+7 −14
Original line number Diff line number Diff line
@@ -88,19 +88,11 @@ struct clk_hw { 
 * 		array index into the value programmed into the hardware.

 * 		Returns 0 on success, -EERROR otherwise.

 *

 * @set_rate:	Change the rate of this clock. If this callback returns

 * 		CLK_SET_RATE_PARENT, the rate change will be propagated to the

 * 		parent clock (which may propagate again if the parent clock

 * 		also sets this flag). The requested rate of the parent is

 * 		passed back from the callback in the second 'unsigned long *'

 * 		argument.  Note that it is up to the hardware clock's set_rate

 * 		implementation to insure that clocks do not run out of spec

 * 		when propgating the call to set_rate up to the parent.  One way

 * 		to do this is to gate the clock (via clk_disable and/or

 * 		clk_unprepare) before calling clk_set_rate, then ungating it

 * 		afterward.  If your clock also has the CLK_GATE_SET_RATE flag

 * 		set then this will insure safety.  Returns 0 on success,

 * 		-EERROR otherwise.

 * @set_rate:	Change the rate of this clock. The requested rate is specified

 *		by the second argument, which should typically be the return

 *		of .round_rate call.  The third argument gives the parent rate

 *		which is likely helpful for most .set_rate implementation.

 *		Returns 0 on success, -EERROR otherwise.

 *

 * The clk_enable/clk_disable and clk_prepare/clk_unprepare pairs allow

 * implementations to split any work between atomic (enable) and sleepable
@@ -125,7 +117,8 @@ struct clk_ops { 
					unsigned long *);

	int		(*set_parent)(struct clk_hw *hw, u8 index);

	u8		(*get_parent)(struct clk_hw *hw);

	int		(*set_rate)(struct clk_hw *hw, unsigned long);

	int		(*set_rate)(struct clk_hw *hw, unsigned long,

				    unsigned long);

	void		(*init)(struct clk_hw *hw);

};