Merge "clk: qcom: clock: Add Video clock controller driver for MSMSKUNK" into msm-4.8 (1bd4c36c) · Commits · e / devices / android_kernel_fairphone_FP3

Documentation/devicetree/bindings/clock/qcom,videocc.txt

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			Qualcomm Technologies Video Clock & Reset Controller Binding
			----------------------------------------------------

			Required properties :
			- compatible : shall contain "qcom,video_cc-msmskunk"
			- reg : shall contain base register location and length
			- reg-names: names of registers listed in the same order as in
			the reg property.
			- #clock-cells : shall contain 1
			- #reset-cells : shall contain 1

			Optional properties :
			- vdd_<rail>-supply: The logic rail supply.

			Example:
			clock_videocc: qcom,videocc@ab00000 {
			compatible = "qcom,video_cc-msmskunk";
			reg = <0xab00000 0x10000>;
			reg-names = "cc_base";
			vdd_cx-supply = <&pmcobalt_s9_level>;
			#clock-cells = <1>;
			#reset-cells = <1>;
			};

drivers/clk/qcom/Kconfig

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	@@ -159,3 +159,12 @@ config MSM_GCC_SKUNK
	MSMskunk devices.		MSMskunk devices.
	Say Y if you want to use peripheral devices such as UART, SPI,		Say Y if you want to use peripheral devices such as UART, SPI,
	i2c, USB, UFS, SD/eMMC, PCIe, etc.		i2c, USB, UFS, SD/eMMC, PCIe, etc.

			config MSM_VIDEOCC_SKUNK
			tristate "MSMSKUNK Video Clock Controller"
			depends on COMMON_CLK_QCOM
			help
			Support for the video clock controller on Qualcomm Technologies, Inc
			MSMskunk devices.
			Say Y if you want to support video devices and functionality such as
			video encode/decode.

drivers/clk/qcom/Makefile

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	@@ -27,6 +27,7 @@ obj-$(CONFIG_MSM_GCC_8960) += gcc-msm8960.o
	obj-$(CONFIG_MSM_GCC_8974) += gcc-msm8974.o		obj-$(CONFIG_MSM_GCC_8974) += gcc-msm8974.o
	obj-$(CONFIG_MSM_GCC_8996) += gcc-msm8996.o		obj-$(CONFIG_MSM_GCC_8996) += gcc-msm8996.o
	obj-$(CONFIG_MSM_GCC_SKUNK) += gcc-msmskunk.o		obj-$(CONFIG_MSM_GCC_SKUNK) += gcc-msmskunk.o
			obj-$(CONFIG_MSM_VIDEOCC_SKUNK) += videocc-msmskunk.o
	obj-$(CONFIG_MSM_LCC_8960) += lcc-msm8960.o		obj-$(CONFIG_MSM_LCC_8960) += lcc-msm8960.o
	obj-$(CONFIG_MSM_MMCC_8960) += mmcc-msm8960.o		obj-$(CONFIG_MSM_MMCC_8960) += mmcc-msm8960.o
	obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8974.o		obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8974.o

drivers/clk/qcom/videocc-msmskunk.c

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			/*
			* Copyright (c) 2016, The Linux Foundation. All rights reserved.
			*
			* This program is free software; you can redistribute it and/or modify
			* it under the terms of the GNU General Public License version 2 and
			* only version 2 as published by the Free Software Foundation.
			*
			* This program is distributed in the hope that it will be useful,
			* but WITHOUT ANY WARRANTY; without even the implied warranty of
			* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
			* GNU General Public License for more details.
			*/

			#include <linux/kernel.h>
			#include <linux/bitops.h>
			#include <linux/err.h>
			#include <linux/platform_device.h>
			#include <linux/module.h>
			#include <linux/of.h>
			#include <linux/of_device.h>
			#include <linux/clk.h>
			#include <linux/clk-provider.h>
			#include <linux/regmap.h>
			#include <linux/reset-controller.h>

			#include <dt-bindings/clock/qcom,videocc-skunk.h>

			#include "common.h"
			#include "clk-regmap.h"
			#include "clk-pll.h"
			#include "clk-rcg.h"
			#include "clk-branch.h"
			#include "reset.h"
			#include "clk-alpha-pll.h"
			#include "vdd-level-skunk.h"

			#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }

			static DEFINE_VDD_REGULATORS(vdd_cx, VDD_CX_NUM, 1, vdd_corner);

			enum {
			P_BI_TCXO,
			P_CORE_BI_PLL_TEST_SE,
			P_VIDEO_PLL0_OUT_EVEN,
			P_VIDEO_PLL0_OUT_MAIN,
			P_VIDEO_PLL0_OUT_ODD,
			};

			static const struct parent_map video_cc_parent_map_0[] = {
			{ P_BI_TCXO, 0 },
			{ P_VIDEO_PLL0_OUT_MAIN, 1 },
			{ P_VIDEO_PLL0_OUT_EVEN, 2 },
			{ P_VIDEO_PLL0_OUT_ODD, 3 },
			{ P_CORE_BI_PLL_TEST_SE, 4 },
			};

			static const char * const video_cc_parent_names_0[] = {
			"bi_tcxo",
			"video_pll0",
			"video_pll0_out_even",
			"video_pll0_out_odd",
			"core_bi_pll_test_se",
			};

			static struct pll_vco fabia_vco[] = {
			{ 250000000, 2000000000, 0 },
			{ 125000000, 1000000000, 1 },
			};

			static const struct pll_config video_pll0_config = {
			.l = 0x15,
			.frac = 0xaab,
			};

			static struct clk_alpha_pll video_pll0 = {
			.offset = 0x42c,
			.vco_table = fabia_vco,
			.num_vco = ARRAY_SIZE(fabia_vco),
			.type = FABIA_PLL,
			.clkr = {
			.hw.init = &(struct clk_init_data){
			.name = "video_pll0",
			.parent_names = (const char *[]){ "bi_tcxo" },
			.num_parents = 1,
			.ops = &clk_fabia_pll_ops,
			VDD_CX_FMAX_MAP5(
			MIN, 200000000,
			LOW, 660000000,
			LOW_L1, 1212000000,
			NOMINAL, 1332000000,
			HIGH, 1599000000),

			},
			},
			};

			static const struct freq_tbl ftbl_video_cc_venus_clk_src[] = {
			F(101000000, P_VIDEO_PLL0_OUT_MAIN, 4, 0, 0),
			F(202000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
			F(269333333, P_VIDEO_PLL0_OUT_MAIN, 1.5, 0, 0),
			F(404000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
			F(444000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
			F(533000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
			{ }
			};

			static struct clk_rcg2 video_cc_venus_clk_src = {
			.cmd_rcgr = 0x7f0,
			.mnd_width = 0,
			.hid_width = 5,
			.parent_map = video_cc_parent_map_0,
			.freq_tbl = ftbl_video_cc_venus_clk_src,
			.enable_safe_config = true,
			.clkr.hw.init = &(struct clk_init_data){
			.name = "video_cc_venus_clk_src",
			.parent_names = video_cc_parent_names_0,
			.num_parents = 5,
			.flags = CLK_SET_RATE_PARENT,
			.ops = &clk_rcg2_ops,
			VDD_CX_FMAX_MAP6(
			MIN, 100000000,
			LOWER, 200000000,
			LOW, 330000000,
			LOW_L1, 404000000,
			NOMINAL, 444000000,
			HIGH, 533000000),
			},
			};

			static struct clk_branch video_cc_apb_clk = {
			.halt_reg = 0x990,
			.halt_check = BRANCH_HALT,
			.clkr = {
			.enable_reg = 0x990,
			.enable_mask = BIT(0),
			.hw.init = &(struct clk_init_data){
			.name = "video_cc_apb_clk",
			.ops = &clk_branch2_ops,
			},
			},
			};

			static struct clk_branch video_cc_at_clk = {
			.halt_reg = 0x9f0,
			.halt_check = BRANCH_HALT,
			.clkr = {
			.enable_reg = 0x9f0,
			.enable_mask = BIT(0),
			.hw.init = &(struct clk_init_data){
			.name = "video_cc_at_clk",
			.ops = &clk_branch2_ops,
			},
			},
			};

			static struct clk_branch video_cc_debug_clk = {
			.halt_reg = 0xa58,
			.halt_check = BRANCH_HALT,
			.clkr = {
			.enable_reg = 0xa58,
			.enable_mask = BIT(0),
			.hw.init = &(struct clk_init_data){
			.name = "video_cc_debug_clk",
			.ops = &clk_branch2_ops,
			},
			},
			};

			static struct clk_branch video_cc_qdss_trig_clk = {
			.halt_reg = 0x970,
			.halt_check = BRANCH_HALT,
			.clkr = {
			.enable_reg = 0x970,
			.enable_mask = BIT(0),
			.hw.init = &(struct clk_init_data){
			.name = "video_cc_qdss_trig_clk",
			.ops = &clk_branch2_ops,
			},
			},
			};

			static struct clk_branch video_cc_qdss_tsctr_div8_clk = {
			.halt_reg = 0x9d0,
			.halt_check = BRANCH_HALT,
			.clkr = {
			.enable_reg = 0x9d0,
			.enable_mask = BIT(0),
			.hw.init = &(struct clk_init_data){
			.name = "video_cc_qdss_tsctr_div8_clk",
			.ops = &clk_branch2_ops,
			},
			},
			};

			static struct clk_branch video_cc_vcodec0_axi_clk = {
			.halt_reg = 0x930,
			.halt_check = BRANCH_HALT,
			.clkr = {
			.enable_reg = 0x930,
			.enable_mask = BIT(0),
			.hw.init = &(struct clk_init_data){
			.name = "video_cc_vcodec0_axi_clk",
			.ops = &clk_branch2_ops,
			},
			},
			};

			static struct clk_branch video_cc_vcodec0_core_clk = {
			.halt_reg = 0x890,
			.halt_check = BRANCH_VOTED,
			.clkr = {
			.enable_reg = 0x890,
			.enable_mask = BIT(0),
			.hw.init = &(struct clk_init_data){
			.name = "video_cc_vcodec0_core_clk",
			.parent_names = (const char *[]){
			"video_cc_venus_clk_src",
			},
			.num_parents = 1,
			.flags = CLK_SET_RATE_PARENT,
			.ops = &clk_branch2_ops,
			},
			},
			};

			static struct clk_branch video_cc_vcodec1_axi_clk = {
			.halt_reg = 0x950,
			.halt_check = BRANCH_HALT,
			.clkr = {
			.enable_reg = 0x950,
			.enable_mask = BIT(0),
			.hw.init = &(struct clk_init_data){
			.name = "video_cc_vcodec1_axi_clk",
			.ops = &clk_branch2_ops,
			},
			},
			};

			static struct clk_branch video_cc_vcodec1_core_clk = {
			.halt_reg = 0x8d0,
			.halt_check = BRANCH_VOTED,
			.clkr = {
			.enable_reg = 0x8d0,
			.enable_mask = BIT(0),
			.hw.init = &(struct clk_init_data){
			.name = "video_cc_vcodec1_core_clk",
			.parent_names = (const char *[]){
			"video_cc_venus_clk_src",
			},
			.num_parents = 1,
			.flags = CLK_SET_RATE_PARENT,
			.ops = &clk_branch2_ops,
			},
			},
			};

			static struct clk_branch video_cc_venus_ahb_clk = {
			.halt_reg = 0x9b0,
			.halt_check = BRANCH_HALT,
			.clkr = {
			.enable_reg = 0x9b0,
			.enable_mask = BIT(0),
			.hw.init = &(struct clk_init_data){
			.name = "video_cc_venus_ahb_clk",
			.ops = &clk_branch2_ops,
			},
			},
			};

			static struct clk_branch video_cc_venus_ctl_axi_clk = {
			.halt_reg = 0x910,
			.halt_check = BRANCH_HALT,
			.clkr = {
			.enable_reg = 0x910,
			.enable_mask = BIT(0),
			.hw.init = &(struct clk_init_data){
			.name = "video_cc_venus_ctl_axi_clk",
			.ops = &clk_branch2_ops,
			},
			},
			};

			static struct clk_branch video_cc_venus_ctl_core_clk = {
			.halt_reg = 0x850,
			.halt_check = BRANCH_HALT,
			.clkr = {
			.enable_reg = 0x850,
			.enable_mask = BIT(0),
			.hw.init = &(struct clk_init_data){
			.name = "video_cc_venus_ctl_core_clk",
			.parent_names = (const char *[]){
			"video_cc_venus_clk_src",
			},
			.num_parents = 1,
			.flags = CLK_SET_RATE_PARENT,
			.ops = &clk_branch2_ops,
			},
			},
			};

			static struct clk_regmap *video_cc_msmskunk_clocks[] = {
			[VIDEO_CC_APB_CLK] = &video_cc_apb_clk.clkr,
			[VIDEO_CC_AT_CLK] = &video_cc_at_clk.clkr,
			[VIDEO_CC_DEBUG_CLK] = &video_cc_debug_clk.clkr,
			[VIDEO_CC_QDSS_TRIG_CLK] = &video_cc_qdss_trig_clk.clkr,
			[VIDEO_CC_QDSS_TSCTR_DIV8_CLK] = &video_cc_qdss_tsctr_div8_clk.clkr,
			[VIDEO_CC_VCODEC0_AXI_CLK] = &video_cc_vcodec0_axi_clk.clkr,
			[VIDEO_CC_VCODEC0_CORE_CLK] = &video_cc_vcodec0_core_clk.clkr,
			[VIDEO_CC_VCODEC1_AXI_CLK] = &video_cc_vcodec1_axi_clk.clkr,
			[VIDEO_CC_VCODEC1_CORE_CLK] = &video_cc_vcodec1_core_clk.clkr,
			[VIDEO_CC_VENUS_AHB_CLK] = &video_cc_venus_ahb_clk.clkr,
			[VIDEO_CC_VENUS_CLK_SRC] = &video_cc_venus_clk_src.clkr,
			[VIDEO_CC_VENUS_CTL_AXI_CLK] = &video_cc_venus_ctl_axi_clk.clkr,
			[VIDEO_CC_VENUS_CTL_CORE_CLK] = &video_cc_venus_ctl_core_clk.clkr,
			[VIDEO_PLL0] = &video_pll0.clkr,
			};

			static const struct qcom_reset_map video_cc_msmskunk_resets[] = {
			[VIDEO_CC_INTERFACE_BCR] = { 0x8f0 },
			[VIDEO_CC_VCODEC0_BCR] = { 0x870 },
			[VIDEO_CC_VCODEC1_BCR] = { 0x8b0 },
			[VIDEO_CC_VENUS_BCR] = { 0x810 },
			};

			static const struct regmap_config video_cc_msmskunk_regmap_config = {
			.reg_bits = 32,
			.reg_stride = 4,
			.val_bits = 32,
			.max_register = 0xb90,
			.fast_io = true,
			};

			static const struct qcom_cc_desc video_cc_msmskunk_desc = {
			.config = &video_cc_msmskunk_regmap_config,
			.clks = video_cc_msmskunk_clocks,
			.num_clks = ARRAY_SIZE(video_cc_msmskunk_clocks),
			.resets = video_cc_msmskunk_resets,
			.num_resets = ARRAY_SIZE(video_cc_msmskunk_resets),
			};

			static const struct of_device_id video_cc_msmskunk_match_table[] = {
			{ .compatible = "qcom,video_cc-msmskunk" },
			{ }
			};
			MODULE_DEVICE_TABLE(of, video_cc_msmskunk_match_table);

			static int video_cc_msmskunk_probe(struct platform_device *pdev)
			{
			struct regmap *regmap;
			int ret = 0;

			regmap = qcom_cc_map(pdev, &video_cc_msmskunk_desc);
			if (IS_ERR(regmap)) {
			pr_err("Failed to map the Video CC registers\n");
			return PTR_ERR(regmap);
			}

			vdd_cx.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_cx");
			if (IS_ERR(vdd_cx.regulator[0])) {
			if (!(PTR_ERR(vdd_cx.regulator[0]) == -EPROBE_DEFER))
			dev_err(&pdev->dev,
			"Unable to get vdd_cx regulator\n");
			return PTR_ERR(vdd_cx.regulator[0]);
			}

			clk_fabia_pll_configure(&video_pll0, regmap, &video_pll0_config);

			ret = qcom_cc_really_probe(pdev, &video_cc_msmskunk_desc, regmap);
			if (ret) {
			dev_err(&pdev->dev, "Failed to register Video CC clocks\n");
			return ret;
			}

			dev_info(&pdev->dev, "Registered Video CC clocks\n");
			return ret;
			}

			static struct platform_driver video_cc_msmskunk_driver = {
			.probe = video_cc_msmskunk_probe,
			.driver = {
			.name = "video_cc-msmskunk",
			.of_match_table = video_cc_msmskunk_match_table,
			},
			};

			static int __init video_cc_msmskunk_init(void)
			{
			return platform_driver_register(&video_cc_msmskunk_driver);
			}
			core_initcall(video_cc_msmskunk_init);

			static void __exit video_cc_msmskunk_exit(void)
			{
			platform_driver_unregister(&video_cc_msmskunk_driver);
			}
			module_exit(video_cc_msmskunk_exit);

			MODULE_DESCRIPTION("QCOM VIDEO_CC MSMSKUNK Driver");
			MODULE_LICENSE("GPL v2");
			MODULE_ALIAS("platform:video_cc-msmskunk");

include/dt-bindings/clock/qcom,videocc-skunk.h

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	@@ -28,10 +28,6 @@
	#define VIDEO_CC_VENUS_CTL_AXI_CLK 11		#define VIDEO_CC_VENUS_CTL_AXI_CLK 11
	#define VIDEO_CC_VENUS_CTL_CORE_CLK 12		#define VIDEO_CC_VENUS_CTL_CORE_CLK 12
	#define VIDEO_PLL0 13		#define VIDEO_PLL0 13
	#define VIDEO_PLL0_OUT_EVEN 14
	#define VIDEO_PLL0_OUT_MAIN 15
	#define VIDEO_PLL0_OUT_ODD 16
	#define VIDEO_PLL0_OUT_TEST 17

	#define VIDEO_CC_INTERFACE_BCR 0		#define VIDEO_CC_INTERFACE_BCR 0
	#define VIDEO_CC_VCODEC0_BCR 1		#define VIDEO_CC_VCODEC0_BCR 1