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Commit 1ba763d1 authored by Marc Kleine-Budde's avatar Marc Kleine-Budde
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can: flexcan: give member of flexcan_priv holding mailboxes a sensible name 



This patch gives the member of flexcan_priv holding mailboxes a sensible name,
by renaming from "cantxfg" to "mb":

    struct flexcan_priv::cantxfg -> struct flexcan_priv::mb

Signed-off-by: default avatarMarc Kleine-Budde <mkl@pengutronix.de>
parent 89af8746

drivers/net/can/flexcan.c

+13 −13
Original line number Original line Diff line number Diff line
@@ -221,7 +221,7 @@ struct flexcan_regs { 
	u32 rxfgmask;		/* 0x48 */

	u32 rxfgmask;		/* 0x48 */

	u32 rxfir;		/* 0x4c */

	u32 rxfir;		/* 0x4c */

	u32 _reserved3[12];	/* 0x50 */

	u32 _reserved3[12];	/* 0x50 */

	struct flexcan_mb cantxfg[64];	/* 0x80 */

	struct flexcan_mb mb[64];	/* 0x80 */

	/* FIFO-mode:

	/* FIFO-mode:

	 *			MB

	 *			MB

	 * 0x080...0x08f	0	RX message buffer

	 * 0x080...0x08f	0	RX message buffer
@@ -491,25 +491,25 @@ static int flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev) 




	if (cf->can_dlc > 0) {

	if (cf->can_dlc > 0) {

		data = be32_to_cpup((__be32 *)&cf->data[0]);

		data = be32_to_cpup((__be32 *)&cf->data[0]);

		flexcan_write(data, &regs->cantxfg[FLEXCAN_TX_BUF_ID].data[0]);

		flexcan_write(data, &regs->mb[FLEXCAN_TX_BUF_ID].data[0]);

	}

	}

	if (cf->can_dlc > 3) {

	if (cf->can_dlc > 3) {

		data = be32_to_cpup((__be32 *)&cf->data[4]);

		data = be32_to_cpup((__be32 *)&cf->data[4]);

		flexcan_write(data, &regs->cantxfg[FLEXCAN_TX_BUF_ID].data[1]);

		flexcan_write(data, &regs->mb[FLEXCAN_TX_BUF_ID].data[1]);

	}

	}





	can_put_echo_skb(skb, dev, 0);

	can_put_echo_skb(skb, dev, 0);





	flexcan_write(can_id, &regs->cantxfg[FLEXCAN_TX_BUF_ID].can_id);

	flexcan_write(can_id, &regs->mb[FLEXCAN_TX_BUF_ID].can_id);

	flexcan_write(ctrl, &regs->cantxfg[FLEXCAN_TX_BUF_ID].can_ctrl);

	flexcan_write(ctrl, &regs->mb[FLEXCAN_TX_BUF_ID].can_ctrl);





	/* Errata ERR005829 step8:

	/* Errata ERR005829 step8:

	 * Write twice INACTIVE(0x8) code to first MB.

	 * Write twice INACTIVE(0x8) code to first MB.

	 */

	 */

	flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,

	flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,

		      &regs->cantxfg[FLEXCAN_TX_BUF_RESERVED].can_ctrl);

		      &regs->mb[FLEXCAN_TX_BUF_RESERVED].can_ctrl);

	flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,

	flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,

		      &regs->cantxfg[FLEXCAN_TX_BUF_RESERVED].can_ctrl);

		      &regs->mb[FLEXCAN_TX_BUF_RESERVED].can_ctrl);





	return NETDEV_TX_OK;

	return NETDEV_TX_OK;

}

}
@@ -629,7 +629,7 @@ static void flexcan_read_fifo(const struct net_device *dev, 
{

{

	const struct flexcan_priv *priv = netdev_priv(dev);

	const struct flexcan_priv *priv = netdev_priv(dev);

	struct flexcan_regs __iomem *regs = priv->regs;

	struct flexcan_regs __iomem *regs = priv->regs;

	struct flexcan_mb __iomem *mb = &regs->cantxfg[0];

	struct flexcan_mb __iomem *mb = &regs->mb[0];

	u32 reg_ctrl, reg_id;

	u32 reg_ctrl, reg_id;





	reg_ctrl = flexcan_read(&mb->can_ctrl);

	reg_ctrl = flexcan_read(&mb->can_ctrl);
@@ -761,7 +761,7 @@ static irqreturn_t flexcan_irq(int irq, void *dev_id) 




		/* after sending a RTR frame MB is in RX mode */

		/* after sending a RTR frame MB is in RX mode */

		flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,

		flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,

			      &regs->cantxfg[FLEXCAN_TX_BUF_ID].can_ctrl);

			      &regs->mb[FLEXCAN_TX_BUF_ID].can_ctrl);

		flexcan_write((1 << FLEXCAN_TX_BUF_ID), &regs->iflag1);

		flexcan_write((1 << FLEXCAN_TX_BUF_ID), &regs->iflag1);

		netif_wake_queue(dev);

		netif_wake_queue(dev);

	}

	}
@@ -882,18 +882,18 @@ static int flexcan_chip_start(struct net_device *dev) 
	flexcan_write(reg_ctrl, &regs->ctrl);

	flexcan_write(reg_ctrl, &regs->ctrl);





	/* clear and invalidate all mailboxes first */

	/* clear and invalidate all mailboxes first */

	for (i = FLEXCAN_TX_BUF_ID; i < ARRAY_SIZE(regs->cantxfg); i++) {

	for (i = FLEXCAN_TX_BUF_ID; i < ARRAY_SIZE(regs->mb); i++) {

		flexcan_write(FLEXCAN_MB_CODE_RX_INACTIVE,

		flexcan_write(FLEXCAN_MB_CODE_RX_INACTIVE,

			      &regs->cantxfg[i].can_ctrl);

			      &regs->mb[i].can_ctrl);

	}

	}





	/* Errata ERR005829: mark first TX mailbox as INACTIVE */

	/* Errata ERR005829: mark first TX mailbox as INACTIVE */

	flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,

	flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,

		      &regs->cantxfg[FLEXCAN_TX_BUF_RESERVED].can_ctrl);

		      &regs->mb[FLEXCAN_TX_BUF_RESERVED].can_ctrl);





	/* mark TX mailbox as INACTIVE */

	/* mark TX mailbox as INACTIVE */

	flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,

	flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,

		      &regs->cantxfg[FLEXCAN_TX_BUF_ID].can_ctrl);

		      &regs->mb[FLEXCAN_TX_BUF_ID].can_ctrl);





	/* acceptance mask/acceptance code (accept everything) */

	/* acceptance mask/acceptance code (accept everything) */

	flexcan_write(0x0, &regs->rxgmask);

	flexcan_write(0x0, &regs->rxgmask);