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Commit 1b62b611 authored by Thierry Reding's avatar Thierry Reding Committed by Stephen Warren
Browse files

ARM: tegra: Add Tegra20 PCIe support to DT 



Add the top-level pcie-controller node for the Tegra20 SoC. Tegra20 has
two root ports that can use different lane layouts.

Signed-off-by: default avatarThierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
[swarren: split DT changes into a separate patch from the main driver]
Signed-off-by: default avatarStephen Warren <swarren@nvidia.com>
parent 47d2d63b

arch/arm/boot/dts/tegra20.dtsi

+55 −0
Original line number Original line Diff line number Diff line
@@ -455,6 +455,61 @@ 
		#size-cells = <0>;

		#size-cells = <0>;

	};

	};





	pcie-controller {

		compatible = "nvidia,tegra20-pcie";

		device_type = "pci";

		reg = <0x80003000 0x00000800   /* PADS registers */

		       0x80003800 0x00000200   /* AFI registers */

		       0x90000000 0x10000000>; /* configuration space */

		reg-names = "pads", "afi", "cs";

		interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH   /* controller interrupt */

			      GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */

		interrupt-names = "intr", "msi";



		bus-range = <0x00 0xff>;

		#address-cells = <3>;

		#size-cells = <2>;



		ranges = <0x82000000 0 0x80000000 0x80000000 0 0x00001000   /* port 0 registers */

			  0x82000000 0 0x80001000 0x80001000 0 0x00001000   /* port 1 registers */

			  0x81000000 0 0          0x82000000 0 0x00010000   /* downstream I/O */

			  0x82000000 0 0xa0000000 0xa0000000 0 0x10000000   /* non-prefetchable memory */

			  0xc2000000 0 0xb0000000 0xb0000000 0 0x10000000>; /* prefetchable memory */



		clocks = <&tegra_car TEGRA20_CLK_PEX>,

			 <&tegra_car TEGRA20_CLK_AFI>,

			 <&tegra_car TEGRA20_CLK_PCIE_XCLK>,

			 <&tegra_car TEGRA20_CLK_PLL_E>;

		clock-names = "pex", "afi", "pcie_xclk", "pll_e";

		status = "disabled";



		pci@1,0 {

			device_type = "pci";

			assigned-addresses = <0x82000800 0 0x80000000 0 0x1000>;

			reg = <0x000800 0 0 0 0>;

			status = "disabled";



			#address-cells = <3>;

			#size-cells = <2>;

			ranges;



			nvidia,num-lanes = <2>;

		};



		pci@2,0 {

			device_type = "pci";

			assigned-addresses = <0x82001000 0 0x80001000 0 0x1000>;

			reg = <0x001000 0 0 0 0>;

			status = "disabled";



			#address-cells = <3>;

			#size-cells = <2>;

			ranges;



			nvidia,num-lanes = <2>;

		};

	};



	usb@c5000000 {

	usb@c5000000 {

		compatible = "nvidia,tegra20-ehci", "usb-ehci";

		compatible = "nvidia,tegra20-ehci", "usb-ehci";

		reg = <0xc5000000 0x4000>;

		reg = <0xc5000000 0x4000>;