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Commit 1b195916 authored by Eugene Surovegin's avatar Eugene Surovegin Committed by Jeff Garzik
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[PATCH] PPC 44x EMAC driver: add 440GR support 



Add PowerPC 440GR support

Signed-off-by: default avatarStefan Roese <sr@denx.de>
Signed-off-by: default avatarEugene Surovegin <ebs@ebshome.net>
Signed-off-by: default avatarJeff Garzik <jgarzik@pobox.com>
parent 7ad8a89c

drivers/net/Kconfig

+1 −1
Original line number Diff line number Diff line
@@ -1203,7 +1203,7 @@ config IBM_EMAC_RX_SKB_HEADROOM 


config IBM_EMAC_PHY_RX_CLK_FIX

	bool "PHY Rx clock workaround"

	depends on IBM_EMAC && (405EP || 440GX || 440EP)

	depends on IBM_EMAC && (405EP || 440GX || 440EP || 440GR)

	help

	  Enable this if EMAC attached to a PHY which doesn't generate

	  RX clock if there is no link, if this is the case, you will

drivers/net/ibm_emac/ibm_emac.h

+2 −1
Original line number Diff line number Diff line
@@ -26,7 +26,8 @@ 
/* This is a simple check to prevent use of this driver on non-tested SoCs */

#if !defined(CONFIG_405GP) && !defined(CONFIG_405GPR) && !defined(CONFIG_405EP) && \

    !defined(CONFIG_440GP) && !defined(CONFIG_440GX) && !defined(CONFIG_440SP) && \

    !defined(CONFIG_440EP) && !defined(CONFIG_NP405H) && !defined(CONFIG_440SPE)

    !defined(CONFIG_440EP) && !defined(CONFIG_NP405H) && !defined(CONFIG_440SPE) && \

    !defined(CONFIG_440GR)

#error	"Unknown SoC. Please, check chip user manual and make sure EMAC defines are OK"

#endif

drivers/net/ibm_emac/ibm_emac_core.c

+4 −3
Original line number Diff line number Diff line
@@ -87,10 +87,11 @@ MODULE_LICENSE("GPL"); 
 */

static u32 busy_phy_map;



#if defined(CONFIG_IBM_EMAC_PHY_RX_CLK_FIX) && (defined(CONFIG_405EP) || defined(CONFIG_440EP))

#if defined(CONFIG_IBM_EMAC_PHY_RX_CLK_FIX) && \

    (defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR))

/* 405EP has "EMAC to PHY Control Register" (CPC0_EPCTL) which can help us

 * with PHY RX clock problem.

 * 440EP has more sane SDR0_MFR register implementation than 440GX, which

 * 440EP/440GR has more sane SDR0_MFR register implementation than 440GX, which

 * also allows controlling each EMAC clock

 */

static inline void EMAC_RX_CLK_TX(int idx)
@@ -100,7 +101,7 @@ static inline void EMAC_RX_CLK_TX(int idx) 


#if defined(CONFIG_405EP)

	mtdcr(0xf3, mfdcr(0xf3) | (1 << idx));

#else /* CONFIG_440EP */

#else /* CONFIG_440EP || CONFIG_440GR */

	SDR_WRITE(DCRN_SDR_MFR, SDR_READ(DCRN_SDR_MFR) | (0x08000000 >> idx));

#endif

drivers/net/ibm_emac/ibm_emac_mal.h

+1 −1
Original line number Diff line number Diff line
@@ -32,7 +32,7 @@ 
 * reflect the fact that 40x and 44x have slightly different MALs. --ebs

 */

#if defined(CONFIG_405GP) || defined(CONFIG_405GPR) || defined(CONFIG_405EP) || \

    defined(CONFIG_440EP) || defined(CONFIG_NP405H)

    defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_NP405H)

#define MAL_VERSION		1

#elif defined(CONFIG_440GP) || defined(CONFIG_440GX) || defined(CONFIG_440SP) || \

      defined(CONFIG_440SPE)