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Commit 1b07e04e authored by Zhao Yakui's avatar Zhao Yakui Committed by Eric Anholt
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drm/i915: Fix fifo size for self-refresh watermark on 965G 



The total self-refresh fifo entry size for display plane is 512
instead of 128 for 965G. Also fix WM value mask for 965G.

About 1.0W power can be saved on one T61 laptop after the self-refresh
watermark is configured correctly.

Signed-off-by: default avatarZhao Yakui <yakui.zhao@intel.com>
Signed-off-by: default avatarZhenyu wang <zhenyuw@linux.intel.com>
Signed-off-by: default avatarEric Anholt <eric@anholt.net>
parent fa143215

drivers/gpu/drm/i915/i915_reg.h

+2 −1
Original line number Original line Diff line number Diff line
@@ -2140,7 +2140,8 @@ 
#define I830_FIFO_LINE_SIZE	32

#define I830_FIFO_LINE_SIZE	32





#define G4X_FIFO_SIZE		127

#define G4X_FIFO_SIZE		127

#define I945_FIFO_SIZE		127 /* 945 & 965 */

#define I965_FIFO_SIZE		512

#define I945_FIFO_SIZE		127

#define I915_FIFO_SIZE		95

#define I915_FIFO_SIZE		95

#define I855GM_FIFO_SIZE	127 /* In cachelines */

#define I855GM_FIFO_SIZE	127 /* In cachelines */

#define I830_FIFO_SIZE		95

#define I830_FIFO_SIZE		95

drivers/gpu/drm/i915/intel_display.c

+2 −2
Original line number Original line Diff line number Diff line
@@ -2970,10 +2970,10 @@ static void i965_update_wm(struct drm_device *dev, int planea_clock, 
			      pixel_size * sr_hdisplay;

			      pixel_size * sr_hdisplay;

		sr_entries = roundup(sr_entries / I915_FIFO_LINE_SIZE, 1);

		sr_entries = roundup(sr_entries / I915_FIFO_LINE_SIZE, 1);

		DRM_DEBUG("self-refresh entries: %d\n", sr_entries);

		DRM_DEBUG("self-refresh entries: %d\n", sr_entries);

		srwm = I945_FIFO_SIZE - sr_entries;

		srwm = I965_FIFO_SIZE - sr_entries;

		if (srwm < 0)

		if (srwm < 0)

			srwm = 1;

			srwm = 1;

		srwm &= 0x3f;

		srwm &= 0x1ff;

		if (IS_I965GM(dev))

		if (IS_I965GM(dev))

			I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);

			I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);

	} else {

	} else {