Loading drivers/mmc/host/Kconfig +1 −1 Original line number Diff line number Diff line Loading @@ -397,7 +397,7 @@ config MMC_ATMELMCI config MMC_SDHCI_MSM tristate "Qualcomm SDHCI Controller Support" depends on ARCH_QCOM || (ARM && COMPILE_TEST) depends on ARCH_QCOM || ARCH_MSM || (ARM && COMPILE_TEST) depends on MMC_SDHCI_PLTFM help This selects the Secure Digital Host Controller Interface (SDHCI) Loading drivers/mmc/host/sdhci-msm.c +12 −4 Original line number Diff line number Diff line Loading @@ -31,6 +31,8 @@ #define HC_MODE_EN 0x1 #define CORE_POWER 0x0 #define CORE_SW_RST BIT(7) #define CORE_HC_SELECT_IN_EN (1 << 18) #define CORE_HC_SELECT_IN_MASK (7 << 19) #define CORE_PWRCTL_STATUS 0xdc #define CORE_PWRCTL_MASK 0xe0 Loading Loading @@ -506,7 +508,7 @@ static irqreturn_t sdhci_msm_pwr_irq(int irq, void *data) } static const struct of_device_id sdhci_msm_dt_match[] = { { .compatible = "qcom,sdhci-msm-v4" }, { .compatible = "qcom,sdhci-msm" }, {}, }; Loading Loading @@ -555,7 +557,7 @@ static int sdhci_msm_probe(struct platform_device *pdev) sdhci_get_of_property(pdev); /* Setup SDCC bus voter clock. */ msm_host->bus_clk = devm_clk_get(&pdev->dev, "bus"); msm_host->bus_clk = devm_clk_get(&pdev->dev, "bus_clk"); if (!IS_ERR(msm_host->bus_clk)) { /* Vote for max. clk rate for max. performance */ ret = clk_set_rate(msm_host->bus_clk, INT_MAX); Loading @@ -567,7 +569,7 @@ static int sdhci_msm_probe(struct platform_device *pdev) } /* Setup main peripheral bus clock */ msm_host->pclk = devm_clk_get(&pdev->dev, "iface"); msm_host->pclk = devm_clk_get(&pdev->dev, "iface_clk"); if (IS_ERR(msm_host->pclk)) { ret = PTR_ERR(msm_host->pclk); dev_err(&pdev->dev, "Peripheral clk setup failed (%d)\n", ret); Loading @@ -579,7 +581,7 @@ static int sdhci_msm_probe(struct platform_device *pdev) goto bus_clk_disable; /* Setup SDC MMC clock */ msm_host->clk = devm_clk_get(&pdev->dev, "core"); msm_host->clk = devm_clk_get(&pdev->dev, "core_clk"); if (IS_ERR(msm_host->clk)) { ret = PTR_ERR(msm_host->clk); dev_err(&pdev->dev, "SDC MMC clk setup failed (%d)\n", ret); Loading @@ -604,6 +606,12 @@ static int sdhci_msm_probe(struct platform_device *pdev) goto clk_disable; } /* Disable mode selection via the vendor specific register */ writel_relaxed((readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC) & ~CORE_HC_SELECT_IN_EN & ~CORE_HC_SELECT_IN_MASK), host->ioaddr + CORE_VENDOR_SPEC); /* Reset the core and Enable SDHC mode */ writel_relaxed(readl_relaxed(msm_host->core_mem + CORE_POWER) | CORE_SW_RST, msm_host->core_mem + CORE_POWER); Loading Loading
drivers/mmc/host/Kconfig +1 −1 Original line number Diff line number Diff line Loading @@ -397,7 +397,7 @@ config MMC_ATMELMCI config MMC_SDHCI_MSM tristate "Qualcomm SDHCI Controller Support" depends on ARCH_QCOM || (ARM && COMPILE_TEST) depends on ARCH_QCOM || ARCH_MSM || (ARM && COMPILE_TEST) depends on MMC_SDHCI_PLTFM help This selects the Secure Digital Host Controller Interface (SDHCI) Loading
drivers/mmc/host/sdhci-msm.c +12 −4 Original line number Diff line number Diff line Loading @@ -31,6 +31,8 @@ #define HC_MODE_EN 0x1 #define CORE_POWER 0x0 #define CORE_SW_RST BIT(7) #define CORE_HC_SELECT_IN_EN (1 << 18) #define CORE_HC_SELECT_IN_MASK (7 << 19) #define CORE_PWRCTL_STATUS 0xdc #define CORE_PWRCTL_MASK 0xe0 Loading Loading @@ -506,7 +508,7 @@ static irqreturn_t sdhci_msm_pwr_irq(int irq, void *data) } static const struct of_device_id sdhci_msm_dt_match[] = { { .compatible = "qcom,sdhci-msm-v4" }, { .compatible = "qcom,sdhci-msm" }, {}, }; Loading Loading @@ -555,7 +557,7 @@ static int sdhci_msm_probe(struct platform_device *pdev) sdhci_get_of_property(pdev); /* Setup SDCC bus voter clock. */ msm_host->bus_clk = devm_clk_get(&pdev->dev, "bus"); msm_host->bus_clk = devm_clk_get(&pdev->dev, "bus_clk"); if (!IS_ERR(msm_host->bus_clk)) { /* Vote for max. clk rate for max. performance */ ret = clk_set_rate(msm_host->bus_clk, INT_MAX); Loading @@ -567,7 +569,7 @@ static int sdhci_msm_probe(struct platform_device *pdev) } /* Setup main peripheral bus clock */ msm_host->pclk = devm_clk_get(&pdev->dev, "iface"); msm_host->pclk = devm_clk_get(&pdev->dev, "iface_clk"); if (IS_ERR(msm_host->pclk)) { ret = PTR_ERR(msm_host->pclk); dev_err(&pdev->dev, "Peripheral clk setup failed (%d)\n", ret); Loading @@ -579,7 +581,7 @@ static int sdhci_msm_probe(struct platform_device *pdev) goto bus_clk_disable; /* Setup SDC MMC clock */ msm_host->clk = devm_clk_get(&pdev->dev, "core"); msm_host->clk = devm_clk_get(&pdev->dev, "core_clk"); if (IS_ERR(msm_host->clk)) { ret = PTR_ERR(msm_host->clk); dev_err(&pdev->dev, "SDC MMC clk setup failed (%d)\n", ret); Loading @@ -604,6 +606,12 @@ static int sdhci_msm_probe(struct platform_device *pdev) goto clk_disable; } /* Disable mode selection via the vendor specific register */ writel_relaxed((readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC) & ~CORE_HC_SELECT_IN_EN & ~CORE_HC_SELECT_IN_MASK), host->ioaddr + CORE_VENDOR_SPEC); /* Reset the core and Enable SDHC mode */ writel_relaxed(readl_relaxed(msm_host->core_mem + CORE_POWER) | CORE_SW_RST, msm_host->core_mem + CORE_POWER); Loading