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Commit 1aa844cd authored by Ben Zhang's avatar Ben Zhang Committed by Mark Brown
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ASoC: rt5677: Reconfigure PLL1 after resume 



Sometimes PLL1 stops working if the codec loses power
during suspend (when pow-ldo2 or reset gpio is used).
MX-7Bh(RT5677_PLL1_CTRL2) is cleared and won't be restored
by regcache since it's volatile. MX-7Bh has one status bit
and M code for PLL1. rt5677_set_dai_pll doesn't reconfigure
PLL1 after resume because it thinks the PLL params are not
changed.

This patch clears the cached PLL params at resume so that
rt5677_set_dai_pll can reconfigure the PLL after resume.

Signed-off-by: default avatarBen Zhang <benzh@chromium.org>
Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent cdab0d4e

sound/soc/codecs/rt5677.c

+3 −0
Original line number Diff line number Diff line
@@ -4792,6 +4792,9 @@ static int rt5677_resume(struct snd_soc_codec *codec) 
	struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);



	if (!rt5677->dsp_vad_en) {

		rt5677->pll_src = 0;

		rt5677->pll_in = 0;

		rt5677->pll_out = 0;

		gpiod_set_value_cansleep(rt5677->pow_ldo2, 1);

		gpiod_set_value_cansleep(rt5677->reset_pin, 0);

		if (rt5677->pow_ldo2 || rt5677->reset_pin)