Merge "mmc: host: sdhci-msm-ice: Support for clearing ice configuration" (1a81004b) · Commits · e / devices / android_kernel_fairphone_FP3

drivers/mmc/host/cmdq_hci.c

+17 −3

Original line number	Diff line number	Diff line
		@@ -220,6 +220,10 @@ static void cmdq_dump_adma_mem(struct cmdq_host *cq_host)
		static void cmdq_dumpregs(struct cmdq_host *cq_host)
		{
		struct mmc_host *mmc = cq_host->mmc;
		int offset = 0;

		if (cq_host->offset_changed)
		offset = CQ_V5_VENDOR_CFG;

		MMC_TRACE(mmc,
		"%s: 0x0C=0x%08x 0x10=0x%08x 0x14=0x%08x 0x18=0x%08x 0x28=0x%08x 0x2C=0x%08x 0x30=0x%08x 0x34=0x%08x 0x54=0x%08x 0x58=0x%08x 0x5C=0x%08x 0x48=0x%08x\n",
		@@ -266,7 +270,7 @@ static void cmdq_dumpregs(struct cmdq_host *cq_host)
		cmdq_readl(cq_host, CQCRI),
		cmdq_readl(cq_host, CQCRA));
		pr_err(DRV_NAME": Vendor cfg 0x%08x\n",
		cmdq_readl(cq_host, CQ_VENDOR_CFG));
		cmdq_readl(cq_host, CQ_VENDOR_CFG + offset));
		pr_err(DRV_NAME ": ===========================================\n");

		cmdq_dump_task_history(cq_host);
		@@ -407,6 +411,12 @@ static int cmdq_enable(struct mmc_host *mmc)
		cq_host->caps \|= CMDQ_CAP_CRYPTO_SUPPORT \|
		CMDQ_TASK_DESC_SZ_128;
		cqcfg \|= CQ_ICE_ENABLE;
		/*
		* For SDHC v5.0 onwards, ICE 3.0 specific registers are added
		* in CQ register space, due to which few CQ registers are
		* shifted. Set offset_changed boolean to use updated address.
		*/
		cq_host->offset_changed = true;
		}

		cmdq_writel(cq_host, cqcfg, CQCFG);
		@@ -841,14 +851,18 @@ static void cmdq_finish_data(struct mmc_host *mmc, unsigned int tag)
		{
		struct mmc_request *mrq;
		struct cmdq_host cq_host = (struct cmdq_host )mmc_cmdq_private(mmc);
		int offset = 0;

		if (cq_host->offset_changed)
		offset = CQ_V5_VENDOR_CFG;
		mrq = get_req_by_tag(cq_host, tag);
		if (tag == cq_host->dcmd_slot)
		mrq->cmd->resp[0] = cmdq_readl(cq_host, CQCRDCT);

		if (mrq->cmdq_req->cmdq_req_flags & DCMD)
		cmdq_writel(cq_host, cmdq_readl(cq_host, CQ_VENDOR_CFG) \|
		CMDQ_SEND_STATUS_TRIGGER, CQ_VENDOR_CFG);
		cmdq_writel(cq_host,
		cmdq_readl(cq_host, CQ_VENDOR_CFG + offset) \|
		CMDQ_SEND_STATUS_TRIGGER, CQ_VENDOR_CFG + offset);

		cmdq_runtime_pm_put(cq_host);
		if (!(cq_host->caps & CMDQ_CAP_CRYPTO_SUPPORT) &&

drivers/mmc/host/cmdq_hci.h

+6 −0

Original line number	Diff line number	Diff line
		@@ -145,6 +145,11 @@
		#define DAT_ADDR_LO(x) ((x & 0xFFFFFFFF) << 32)
		#define DAT_ADDR_HI(x) ((x & 0xFFFFFFFF) << 0)

		/*
		* Add new macro for updated CQ vendor specific
		* register address for SDHC v5.0 onwards.
		*/
		#define CQ_V5_VENDOR_CFG 0x900
		#define CQ_VENDOR_CFG 0x100
		#define CMDQ_SEND_STATUS_TRIGGER (1 << 31)

		@@ -177,6 +182,7 @@ struct cmdq_host {
		bool enabled;
		bool halted;
		bool init_done;
		bool offset_changed;

		u8 *desc_base;

drivers/mmc/host/sdhci-msm-ice.c

+31 −0

Original line number	Diff line number	Diff line
		@@ -414,6 +414,37 @@ int sdhci_msm_ice_cmdq_cfg(struct sdhci_host *host,
		return 0;
		}

		int sdhci_msm_ice_cfg_end(struct sdhci_host host, struct mmc_request mrq)
		{
		struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
		struct sdhci_msm_host *msm_host = pltfm_host->priv;
		int err = 0;
		struct request *req;

		if (!host->is_crypto_en)
		return 0;

		if (msm_host->ice.state != SDHCI_MSM_ICE_STATE_ACTIVE) {
		pr_err("%s: ice is in invalid state %d\n",
		mmc_hostname(host->mmc), msm_host->ice.state);
		return -EINVAL;
		}

		req = mrq->req;
		if (req) {
		if (msm_host->ice.vops->config_end) {
		err = msm_host->ice.vops->config_end(req);
		if (err) {
		pr_err("%s: ice config end failed %d\n",
		mmc_hostname(host->mmc), err);
		return err;
		}
		}
		}

		return 0;
		}

		int sdhci_msm_ice_reset(struct sdhci_host *host)
		{
		struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);

drivers/mmc/host/sdhci-msm-ice.h

+6 −0

Original line number	Diff line number	Diff line
		@@ -107,6 +107,7 @@ int sdhci_msm_ice_cfg(struct sdhci_host host, struct mmc_request mrq,
		u32 slot);
		int sdhci_msm_ice_cmdq_cfg(struct sdhci_host *host,
		struct mmc_request mrq, u32 slot, u64 ice_ctx);
		int sdhci_msm_ice_cfg_end(struct sdhci_host host, struct mmc_request mrq);
		int sdhci_msm_ice_reset(struct sdhci_host *host);
		int sdhci_msm_ice_resume(struct sdhci_host *host);
		int sdhci_msm_ice_suspend(struct sdhci_host *host);
		@@ -143,6 +144,11 @@ static inline int sdhci_msm_ice_cmdq_cfg(struct sdhci_host *host,
		{
		return 0;
		}
		static inline int sdhci_msm_ice_cfg_end(struct sdhci_host *host,
		struct mmc_request *mrq)
		{
		return 0;
		}
		inline int sdhci_msm_ice_reset(struct sdhci_host *host)
		{
		return 0;

drivers/mmc/host/sdhci-msm.c

+3 −0

Original line number	Diff line number	Diff line
		@@ -3408,6 +3408,8 @@ static void sdhci_msm_cmdq_dump_debug_ram(struct sdhci_host *host)
		/* registers offset changed starting from 4.2.0 */
		int offset = minor >= SDHCI_MSM_VER_420 ? 0 : 0x48;

		if (cq_host->offset_changed)
		offset += CQ_V5_VENDOR_CFG;
		pr_err("---- Debug RAM dump ----\n");
		pr_err(DRV_NAME ": Debug RAM wrap-around: 0x%08x \| Debug RAM overlap: 0x%08x\n",
		cmdq_readl(cq_host, CQ_CMD_DBG_RAM_WA + offset),
		@@ -4116,6 +4118,7 @@ static unsigned int sdhci_msm_get_current_limit(struct sdhci_host *host)
		static struct sdhci_ops sdhci_msm_ops = {
		.crypto_engine_cfg = sdhci_msm_ice_cfg,
		.crypto_engine_cmdq_cfg = sdhci_msm_ice_cmdq_cfg,
		.crypto_engine_cfg_end = sdhci_msm_ice_cfg_end,
		.crypto_cfg_reset = sdhci_msm_ice_cfg_reset,
		.crypto_engine_reset = sdhci_msm_ice_reset,
		.set_uhs_signaling = sdhci_msm_set_uhs_signaling,