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Commit 1a647276 authored by Deepak Katragadda's avatar Deepak Katragadda
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clk: qcom: gcc-sdm845: Add reset clock registers for PCIE PHY on SDM845 



Add the missing PCIE PHY BCR register modelling on SDM845.

Change-Id: I6791abaaf56d3fb5181126516d1c911117ac0444
Signed-off-by: default avatarDeepak Katragadda <dkatraga@codeaurora.org>
parent 925b2207

drivers/clk/qcom/gcc-sdm845.c

+2 −0
Original line number Diff line number Diff line
@@ -3332,6 +3332,8 @@ static const struct qcom_reset_map gcc_sdm845_resets[] = { 
	[GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 },

	[GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 },

	[GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },

	[GCC_PCIE_0_PHY_BCR] = { 0x6c01c },

	[GCC_PCIE_1_PHY_BCR] = { 0x8e01c },

};



static const struct regmap_config gcc_sdm845_regmap_config = {

include/dt-bindings/clock/qcom,gcc-sdm845.h

+2 −0
Original line number Diff line number Diff line
@@ -217,6 +217,8 @@ 
#define GCC_USB3PHY_PHY_SEC_BCR					22

#define GCC_USB3_DP_PHY_SEC_BCR					23

#define GCC_USB_PHY_CFG_AHB2PHY_BCR				24

#define GCC_PCIE_0_PHY_BCR					25

#define GCC_PCIE_1_PHY_BCR					26



/* Dummy clocks for rate measurement */

#define MEASURE_ONLY_SNOC_CLK					0