Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 19c03924 authored by Gajanan Bhat's avatar Gajanan Bhat Committed by Daniel Vetter
Browse files

drm/i915: Add eDP support for Valleyview 



Eventhough Valleyview display block is derived from Cantiga, VLV
supports eDP. So, added eDP checks in i9xx_crtc_mode_set path.

v2: use different DPIO_DIVISOR values for VGA, DP and eDP
v3: fix DPIO value calculation to use same values for all display
interfaces
v4: removed unconditional enabling of 6bpc dithering based on comments
from Daniel & Jani Nikula. Also changed the display enabling order to
force eDP detection first.

Signed-off-by: default avatarGajanan Bhat <gajanan.bhat@intel.com>
Signed-off-by: default avatarVijay Purushothaman <vijay.a.purushothaman@intel.com>
Reviewed-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 2a8f64ca

drivers/gpu/drm/i915/intel_display.c

+12 −3
Original line number Diff line number Diff line
@@ -4415,6 +4415,14 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc, 
		}

	}



	if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {

		if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {

			pipeconf |= PIPECONF_BPP_6 |

					PIPECONF_ENABLE |

					I965_PIPECONF_ACTIVE;

		}

	}



	DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');

	drm_mode_debug_printmodeline(mode);
@@ -7673,6 +7681,10 @@ static void intel_setup_outputs(struct drm_device *dev) 
	} else if (IS_VALLEYVIEW(dev)) {

		int found;



		/* Check for built-in panel first. Shares lanes with HDMI on SDVOC */

		if (I915_READ(DP_C) & DP_DETECTED)

			intel_dp_init(dev, DP_C, PORT_C);



		if (I915_READ(SDVOB) & PORT_DETECTED) {

			/* SDVOB multiplex with HDMIB */

			found = intel_sdvo_init(dev, SDVOB, true);
@@ -7685,9 +7697,6 @@ static void intel_setup_outputs(struct drm_device *dev) 
		if (I915_READ(SDVOC) & PORT_DETECTED)

			intel_hdmi_init(dev, SDVOC, PORT_C);



		/* Shares lanes with HDMI on SDVOC */

		if (I915_READ(DP_C) & DP_DETECTED)

			intel_dp_init(dev, DP_C, PORT_C);

	} else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {

		bool found = false;

drivers/gpu/drm/i915/intel_dp.c

+12 −5
Original line number Diff line number Diff line
@@ -886,7 +886,7 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, 


	/* Split out the IBX/CPU vs CPT settings */



	if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) {

	if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {

		if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)

			intel_dp->DP |= DP_SYNC_HS_HIGH;

		if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
@@ -1475,7 +1475,7 @@ intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing) 
{

	struct drm_device *dev = intel_dp->base.base.dev;



	if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {

	if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {

		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {

		case DP_TRAIN_VOLTAGE_SWING_400:

			return DP_TRAIN_PRE_EMPHASIS_6;
@@ -1774,7 +1774,7 @@ intel_dp_start_link_train(struct intel_dp *intel_dp) 
		uint32_t    signal_levels;





		if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {

		if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {

			signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);

			DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;

		} else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
@@ -1860,7 +1860,7 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp) 
			break;

		}



		if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {

		if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {

			signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);

			DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;

		} else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
@@ -2517,7 +2517,14 @@ intel_dp_init(struct drm_device *dev, int output_reg, enum port port) 
		if (intel_dpd_is_edp(dev))

			intel_dp->is_pch_edp = true;



	if (output_reg == DP_A || is_pch_edp(intel_dp)) {

	/*

	 * FIXME : We need to initialize built-in panels before external panels.

	 * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup

	 */

	if (IS_VALLEYVIEW(dev) && output_reg == DP_C) {

		type = DRM_MODE_CONNECTOR_eDP;

		intel_encoder->type = INTEL_OUTPUT_EDP;

	} else if (output_reg == DP_A || is_pch_edp(intel_dp)) {

		type = DRM_MODE_CONNECTOR_eDP;

		intel_encoder->type = INTEL_OUTPUT_EDP;

	} else {