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Commit 1938de46 authored by Mike Hench's avatar Mike Hench Committed by David Woodhouse
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[MTD] [NAND] corrected MPC8313 NAND fixes 



Fix a race condition in fsl_elbc_run_command
Fix incorrect usage of clearbits32 that bashed option register
Remove work around for bashed register

Signed-off-by: default avatarMike Hench <mhench@elutions.com>
Acked-by: default avatarScott Wood <scottwood@freescale.com>
Signed-off-by: default avatarDavid Woodhouse <dwmw2@infradead.org>
parent 9ebed3e6

drivers/mtd/nand/fsl_elbc_nand.c

+2 −7
Original line number Diff line number Diff line
@@ -184,11 +184,11 @@ static int fsl_elbc_run_command(struct mtd_info *mtd) 
	         in_be32(&lbc->fbar), in_be32(&lbc->fpar),

	         in_be32(&lbc->fbcr), priv->bank);



	ctrl->irq_status = 0;

	/* execute special operation */

	out_be32(&lbc->lsor, priv->bank);



	/* wait for FCM complete flag or timeout */

	ctrl->irq_status = 0;

	wait_event_timeout(ctrl->irq_wait, ctrl->irq_status,

	                   FCM_TIMEOUT_MSECS * HZ/1000);

	ctrl->status = ctrl->irq_status;
@@ -667,7 +667,7 @@ static int fsl_elbc_chip_init_tail(struct mtd_info *mtd) 
	/* adjust Option Register and ECC to match Flash page size */

	if (mtd->writesize == 512) {

		priv->page_size = 0;

		clrbits32(&lbc->bank[priv->bank].or, ~OR_FCM_PGS);

		clrbits32(&lbc->bank[priv->bank].or, OR_FCM_PGS);

	} else if (mtd->writesize == 2048) {

		priv->page_size = 1;

		setbits32(&lbc->bank[priv->bank].or, OR_FCM_PGS);
@@ -688,11 +688,6 @@ static int fsl_elbc_chip_init_tail(struct mtd_info *mtd) 
		return -1;

	}



	/* The default u-boot configuration on MPC8313ERDB causes errors;

	 * more delay is needed.  This should be safe for other boards

	 * as well.

	 */

	setbits32(&lbc->bank[priv->bank].or, 0x70);

	return 0;

}