Merge "Merge android-4.9.109 (a4230be) into msm-4.9" (192abd85) · Commits · e / devices / android_kernel_fairphone_FP3

Documentation/networking/netdev-FAQ.txt

+9 −0

Original line number	Diff line number	Diff line
		@@ -168,6 +168,15 @@ A: No. See above answer. In short, if you think it really belongs in
		dash marker line as described in Documentation/SubmittingPatches to
		temporarily embed that information into the patch that you send.

		Q: Are all networking bug fixes backported to all stable releases?

		A: Due to capacity, Dave could only take care of the backports for the last
		2 stable releases. For earlier stable releases, each stable branch maintainer
		is supposed to take care of them. If you find any patch is missing from an
		earlier stable branch, please notify stable@vger.kernel.org with either a
		commit ID or a formal patch backported, and CC Dave and other relevant
		networking developers.

		Q: Someone said that the comment style and coding convention is different
		for the networking content. Is this true?

Makefile

+1 −1

Original line number	Diff line number	Diff line
		VERSION = 4
		PATCHLEVEL = 9
		SUBLEVEL = 106
		SUBLEVEL = 109
		EXTRAVERSION =
		NAME = Roaring Lionus

arch/arm64/include/asm/atomic_lse.h

+11 −11

Original line number	Diff line number	Diff line
		@@ -117,7 +117,7 @@ static inline void atomic_and(int i, atomic_t *v)
		/* LSE atomics */
		" mvn %w[i], %w[i]\n"
		" stclr %w[i], %[v]")
		: [i] "+r" (w0), [v] "+Q" (v->counter)
		: [i] "+&r" (w0), [v] "+Q" (v->counter)
		: "r" (x1)
		: __LL_SC_CLOBBERS);
		}
		@@ -135,7 +135,7 @@ static inline int atomic_fetch_and##name(int i, atomic_t *v) \
		/* LSE atomics */ \
		" mvn %w[i], %w[i]\n" \
		" ldclr" #mb " %w[i], %w[i], %[v]") \
		: [i] "+r" (w0), [v] "+Q" (v->counter) \
		: [i] "+&r" (w0), [v] "+Q" (v->counter) \
		: "r" (x1) \
		: __LL_SC_CLOBBERS, ##cl); \
		\
		@@ -161,7 +161,7 @@ static inline void atomic_sub(int i, atomic_t *v)
		/* LSE atomics */
		" neg %w[i], %w[i]\n"
		" stadd %w[i], %[v]")
		: [i] "+r" (w0), [v] "+Q" (v->counter)
		: [i] "+&r" (w0), [v] "+Q" (v->counter)
		: "r" (x1)
		: __LL_SC_CLOBBERS);
		}
		@@ -180,7 +180,7 @@ static inline int atomic_sub_return##name(int i, atomic_t *v) \
		" neg %w[i], %w[i]\n" \
		" ldadd" #mb " %w[i], w30, %[v]\n" \
		" add %w[i], %w[i], w30") \
		: [i] "+r" (w0), [v] "+Q" (v->counter) \
		: [i] "+&r" (w0), [v] "+Q" (v->counter) \
		: "r" (x1) \
		: __LL_SC_CLOBBERS , ##cl); \
		\
		@@ -207,7 +207,7 @@ static inline int atomic_fetch_sub##name(int i, atomic_t *v) \
		/* LSE atomics */ \
		" neg %w[i], %w[i]\n" \
		" ldadd" #mb " %w[i], %w[i], %[v]") \
		: [i] "+r" (w0), [v] "+Q" (v->counter) \
		: [i] "+&r" (w0), [v] "+Q" (v->counter) \
		: "r" (x1) \
		: __LL_SC_CLOBBERS, ##cl); \
		\
		@@ -314,7 +314,7 @@ static inline void atomic64_and(long i, atomic64_t *v)
		/* LSE atomics */
		" mvn %[i], %[i]\n"
		" stclr %[i], %[v]")
		: [i] "+r" (x0), [v] "+Q" (v->counter)
		: [i] "+&r" (x0), [v] "+Q" (v->counter)
		: "r" (x1)
		: __LL_SC_CLOBBERS);
		}
		@@ -332,7 +332,7 @@ static inline long atomic64_fetch_and##name(long i, atomic64_t *v) \
		/* LSE atomics */ \
		" mvn %[i], %[i]\n" \
		" ldclr" #mb " %[i], %[i], %[v]") \
		: [i] "+r" (x0), [v] "+Q" (v->counter) \
		: [i] "+&r" (x0), [v] "+Q" (v->counter) \
		: "r" (x1) \
		: __LL_SC_CLOBBERS, ##cl); \
		\
		@@ -358,7 +358,7 @@ static inline void atomic64_sub(long i, atomic64_t *v)
		/* LSE atomics */
		" neg %[i], %[i]\n"
		" stadd %[i], %[v]")
		: [i] "+r" (x0), [v] "+Q" (v->counter)
		: [i] "+&r" (x0), [v] "+Q" (v->counter)
		: "r" (x1)
		: __LL_SC_CLOBBERS);
		}
		@@ -377,7 +377,7 @@ static inline long atomic64_sub_return##name(long i, atomic64_t *v) \
		" neg %[i], %[i]\n" \
		" ldadd" #mb " %[i], x30, %[v]\n" \
		" add %[i], %[i], x30") \
		: [i] "+r" (x0), [v] "+Q" (v->counter) \
		: [i] "+&r" (x0), [v] "+Q" (v->counter) \
		: "r" (x1) \
		: __LL_SC_CLOBBERS, ##cl); \
		\
		@@ -404,7 +404,7 @@ static inline long atomic64_fetch_sub##name(long i, atomic64_t *v) \
		/* LSE atomics */ \
		" neg %[i], %[i]\n" \
		" ldadd" #mb " %[i], %[i], %[v]") \
		: [i] "+r" (x0), [v] "+Q" (v->counter) \
		: [i] "+&r" (x0), [v] "+Q" (v->counter) \
		: "r" (x1) \
		: __LL_SC_CLOBBERS, ##cl); \
		\
		@@ -516,7 +516,7 @@ static inline long __cmpxchg_double##name(unsigned long old1, \
		" eor %[old1], %[old1], %[oldval1]\n" \
		" eor %[old2], %[old2], %[oldval2]\n" \
		" orr %[old1], %[old1], %[old2]") \
		: [old1] "+r" (x0), [old2] "+r" (x1), \
		: [old1] "+&r" (x0), [old2] "+&r" (x1), \
		[v] "+Q" ((unsigned long )ptr) \
		: [new1] "r" (x2), [new2] "r" (x3), [ptr] "r" (x4), \
		[oldval1] "r" (oldval1), [oldval2] "r" (oldval2) \

arch/arm64/include/asm/cpufeature.h

+20 −7

Original line number	Diff line number	Diff line
		@@ -9,8 +9,6 @@
		#ifndef __ASM_CPUFEATURE_H
		#define __ASM_CPUFEATURE_H

		#include <linux/jump_label.h>

		#include <asm/cpucaps.h>
		#include <asm/hwcap.h>
		#include <asm/sysreg.h>
		@@ -27,6 +25,8 @@

		#ifndef __ASSEMBLY__

		#include <linux/bug.h>
		#include <linux/jump_label.h>
		#include <linux/kernel.h>

		extern const char *machine_name;
		@@ -98,6 +98,7 @@ struct arm64_cpu_capabilities {

		extern DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
		extern struct static_key_false cpu_hwcap_keys[ARM64_NCAPS];
		extern struct static_key_false arm64_const_caps_ready;

		bool this_cpu_has_cap(unsigned int cap);

		@@ -106,16 +107,29 @@ static inline bool cpu_have_feature(unsigned int num)
		return elf_hwcap & (1UL << num);
		}

		static inline bool cpus_have_cap(unsigned int num)
		/* System capability check for constant caps */
		static inline bool __cpus_have_const_cap(int num)
		{
		if (num >= ARM64_NCAPS)
		return false;
		if (__builtin_constant_p(num))
		return static_branch_unlikely(&cpu_hwcap_keys[num]);
		else
		}

		static inline bool cpus_have_cap(unsigned int num)
		{
		if (num >= ARM64_NCAPS)
		return false;
		return test_bit(num, cpu_hwcaps);
		}

		static inline bool cpus_have_const_cap(int num)
		{
		if (static_branch_likely(&arm64_const_caps_ready))
		return __cpus_have_const_cap(num);
		else
		return cpus_have_cap(num);
		}

		static inline void cpus_set_cap(unsigned int num)
		{
		if (num >= ARM64_NCAPS) {
		@@ -123,7 +137,6 @@ static inline void cpus_set_cap(unsigned int num)
		num, ARM64_NCAPS);
		} else {
		__set_bit(num, cpu_hwcaps);
		static_branch_enable(&cpu_hwcap_keys[num]);
		}
		}

		@@ -202,7 +215,7 @@ static inline bool cpu_supports_mixed_endian_el0(void)

		static inline bool system_supports_32bit_el0(void)
		{
		return cpus_have_cap(ARM64_HAS_32BIT_EL0);
		return cpus_have_const_cap(ARM64_HAS_32BIT_EL0);
		}

		static inline bool system_supports_mixed_endian_el0(void)

arch/arm64/include/asm/kvm_host.h

+7 −3

Original line number	Diff line number	Diff line
		@@ -24,6 +24,7 @@

		#include <linux/types.h>
		#include <linux/kvm_types.h>
		#include <asm/cpufeature.h>
		#include <asm/kvm.h>
		#include <asm/kvm_asm.h>
		#include <asm/kvm_mmio.h>
		@@ -358,9 +359,12 @@ static inline void __cpu_init_hyp_mode(phys_addr_t pgd_ptr,
		unsigned long vector_ptr)
		{
		/*
		* Call initialization code, and switch to the full blown
		* HYP code.
		* Call initialization code, and switch to the full blown HYP code.
		* If the cpucaps haven't been finalized yet, something has gone very
		* wrong, and hyp will crash and burn when it uses any
		* cpus_have_const_cap() wrapper.
		*/
		BUG_ON(!static_branch_likely(&arm64_const_caps_ready));
		__kvm_call_hyp((void *)pgd_ptr, hyp_stack_ptr, vector_ptr);
		}

		@@ -398,7 +402,7 @@ static inline void __cpu_init_stage2(void)

		static inline bool kvm_arm_harden_branch_predictor(void)
		{
		return cpus_have_cap(ARM64_HARDEN_BRANCH_PREDICTOR);
		return cpus_have_const_cap(ARM64_HARDEN_BRANCH_PREDICTOR);
		}

		#endif /* __ARM64_KVM_HOST_H__ */