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Commit 1904b034 authored by Wolfgang Grandegger's avatar Wolfgang Grandegger Committed by Ben Dooks
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i2c-mpc: bug fix for MPC52xx clock setting and printout 



The clock setting did not work for the MPC52xx due to a stupid bug.
Furthermore, the dev info output "clock=0" for old device trees was
misleading. This patch fixes both issues.

Signed-off-by: default avatarWolfgang Grandegger <wg@grandegger.com>
Acked-by: default avatarGrant Likely <grant.likely@secretlab.ca>
Signed-off-by: default avatarBen Dooks <ben-linux@fluff.org>
parent d10db3a0

drivers/i2c/busses/i2c-mpc.c

+20 −14
Original line number Original line Diff line number Diff line
@@ -164,7 +164,7 @@ static int i2c_wait(struct mpc_i2c *i2c, unsigned timeout, int writing) 
	return 0;

	return 0;

}

}





#ifdef CONFIG_PPC_52xx

#ifdef CONFIG_PPC_MPC52xx

static const struct mpc_i2c_divider mpc_i2c_dividers_52xx[] = {

static const struct mpc_i2c_divider mpc_i2c_dividers_52xx[] = {

	{20, 0x20}, {22, 0x21}, {24, 0x22}, {26, 0x23},

	{20, 0x20}, {22, 0x21}, {24, 0x22}, {26, 0x23},

	{28, 0x24}, {30, 0x01}, {32, 0x25}, {34, 0x02},

	{28, 0x24}, {30, 0x01}, {32, 0x25}, {34, 0x02},
@@ -188,7 +188,7 @@ static const struct mpc_i2c_divider mpc_i2c_dividers_52xx[] = { 




int mpc_i2c_get_fdr_52xx(struct device_node *node, u32 clock, int prescaler)

int mpc_i2c_get_fdr_52xx(struct device_node *node, u32 clock, int prescaler)

{

{

	const struct mpc52xx_i2c_divider *div = NULL;

	const struct mpc_i2c_divider *div = NULL;

	unsigned int pvr = mfspr(SPRN_PVR);

	unsigned int pvr = mfspr(SPRN_PVR);

	u32 divider;

	u32 divider;

	int i;

	int i;
@@ -203,7 +203,7 @@ int mpc_i2c_get_fdr_52xx(struct device_node *node, u32 clock, int prescaler) 
	 * We want to choose an FDR/DFSR that generates an I2C bus speed that

	 * We want to choose an FDR/DFSR that generates an I2C bus speed that

	 * is equal to or lower than the requested speed.

	 * is equal to or lower than the requested speed.

	 */

	 */

	for (i = 0; i < ARRAY_SIZE(mpc52xx_i2c_dividers); i++) {

	for (i = 0; i < ARRAY_SIZE(mpc_i2c_dividers_52xx); i++) {

		div = &mpc_i2c_dividers_52xx[i];

		div = &mpc_i2c_dividers_52xx[i];

		/* Old MPC5200 rev A CPUs do not support the high bits */

		/* Old MPC5200 rev A CPUs do not support the high bits */

		if (div->fdr & 0xc0 && pvr == 0x80822011)

		if (div->fdr & 0xc0 && pvr == 0x80822011)
@@ -219,20 +219,23 @@ static void mpc_i2c_setclock_52xx(struct device_node *node, 
				  struct mpc_i2c *i2c,

				  struct mpc_i2c *i2c,

				  u32 clock, u32 prescaler)

				  u32 clock, u32 prescaler)

{

{

	int fdr = mpc52xx_i2c_get_fdr(node, clock, prescaler);

	int ret, fdr;



	ret = mpc_i2c_get_fdr_52xx(node, clock, prescaler);

	fdr = (ret >= 0) ? ret : 0x3f; /* backward compatibility */





	if (fdr < 0)

		fdr = 0x3f; /* backward compatibility */

	writeb(fdr & 0xff, i2c->base + MPC_I2C_FDR);

	writeb(fdr & 0xff, i2c->base + MPC_I2C_FDR);



	if (ret >= 0)

		dev_info(i2c->dev, "clock %d Hz (fdr=%d)\n", clock, fdr);

		dev_info(i2c->dev, "clock %d Hz (fdr=%d)\n", clock, fdr);

}

}

#else /* !CONFIG_PPC_52xx */

#else /* !CONFIG_PPC_MPC52xx */

static void mpc_i2c_setclock_52xx(struct device_node *node,

static void mpc_i2c_setclock_52xx(struct device_node *node,

				  struct mpc_i2c *i2c,

				  struct mpc_i2c *i2c,

				  u32 clock, u32 prescaler)

				  u32 clock, u32 prescaler)

{

{

}

}

#endif /* CONFIG_PPC_52xx*/

#endif /* CONFIG_PPC_MPC52xx*/





#ifdef CONFIG_FSL_SOC

#ifdef CONFIG_FSL_SOC

static const struct mpc_i2c_divider mpc_i2c_dividers_8xxx[] = {

static const struct mpc_i2c_divider mpc_i2c_dividers_8xxx[] = {
@@ -321,12 +324,15 @@ static void mpc_i2c_setclock_8xxx(struct device_node *node, 
				  struct mpc_i2c *i2c,

				  struct mpc_i2c *i2c,

				  u32 clock, u32 prescaler)

				  u32 clock, u32 prescaler)

{

{

	int fdr = mpc_i2c_get_fdr_8xxx(node, clock, prescaler);

	int ret, fdr;



	ret = mpc_i2c_get_fdr_8xxx(node, clock, prescaler);

	fdr = (ret >= 0) ? ret : 0x1031; /* backward compatibility */





	if (fdr < 0)

		fdr = 0x1031; /* backward compatibility */

	writeb(fdr & 0xff, i2c->base + MPC_I2C_FDR);

	writeb(fdr & 0xff, i2c->base + MPC_I2C_FDR);

	writeb((fdr >> 8) & 0xff, i2c->base + MPC_I2C_DFSRR);

	writeb((fdr >> 8) & 0xff, i2c->base + MPC_I2C_DFSRR);



	if (ret >= 0)

		dev_info(i2c->dev, "clock %d Hz (dfsrr=%d fdr=%d)\n",

		dev_info(i2c->dev, "clock %d Hz (dfsrr=%d fdr=%d)\n",

			 clock, fdr >> 8, fdr & 0xff);

			 clock, fdr >> 8, fdr & 0xff);

}

}