Loading drivers/iommu/arm-smmu.c +3 −0 Original line number Diff line number Diff line Loading @@ -1713,6 +1713,9 @@ static int arm_smmu_init_domain_context(struct iommu_domain *domain, quirks |= IO_PGTABLE_QUIRK_QCOM_USE_UPSTREAM_HINT; if (is_iommu_pt_coherent(smmu_domain)) quirks |= IO_PGTABLE_QUIRK_PAGE_TABLE_COHERENT; if ((quirks & IO_PGTABLE_QUIRK_QCOM_USE_UPSTREAM_HINT) && (smmu->model == QCOM_SMMUV500)) quirks |= IO_PGTABLE_QUIRK_QSMMUV500_NON_SHAREABLE; tlb = &arm_smmu_gather_ops; if (smmu->options & ARM_SMMU_OPT_QCOM_MMU500_ERRATA1) Loading drivers/iommu/io-pgtable-arm.c +5 −0 Original line number Diff line number Diff line Loading @@ -1011,6 +1011,11 @@ arm_64_lpae_alloc_pgtable_s1(struct io_pgtable_cfg *cfg, void *cookie) reg = (ARM_LPAE_TCR_SH_OS << ARM_LPAE_TCR_SH0_SHIFT) | (ARM_LPAE_TCR_RGN_WBWA << ARM_LPAE_TCR_IRGN0_SHIFT) | (ARM_LPAE_TCR_RGN_WBWA << ARM_LPAE_TCR_ORGN0_SHIFT); else if ((cfg->quirks & IO_PGTABLE_QUIRK_QCOM_USE_UPSTREAM_HINT) && (cfg->quirks & IO_PGTABLE_QUIRK_QSMMUV500_NON_SHAREABLE)) reg = (ARM_LPAE_TCR_SH_NS << ARM_LPAE_TCR_SH0_SHIFT) | (ARM_LPAE_TCR_RGN_NC << ARM_LPAE_TCR_IRGN0_SHIFT) | (ARM_LPAE_TCR_RGN_WBWA << ARM_LPAE_TCR_ORGN0_SHIFT); else if (cfg->quirks & IO_PGTABLE_QUIRK_QCOM_USE_UPSTREAM_HINT) reg = (ARM_LPAE_TCR_SH_OS << ARM_LPAE_TCR_SH0_SHIFT) | (ARM_LPAE_TCR_RGN_NC << ARM_LPAE_TCR_IRGN0_SHIFT) | Loading drivers/iommu/io-pgtable.h +7 −0 Original line number Diff line number Diff line Loading @@ -81,6 +81,12 @@ struct io_pgtable_cfg { * * IO_PGTABLE_QUIRK_PAGE_TABLE_COHERENT: Set the page table as * coherent. * * IO_PGTABLE_QUIRK_QSMMUV500_NON_SHAREABLE: * Having page tables which are non coherent, but cached in a * system cache requires SH=Non-Shareable. This applies to the * qsmmuv500 model. For data buffers SH=Non-Shareable is not * required. */ #define IO_PGTABLE_QUIRK_ARM_NS BIT(0) #define IO_PGTABLE_QUIRK_NO_PERMS BIT(1) Loading @@ -88,6 +94,7 @@ struct io_pgtable_cfg { #define IO_PGTABLE_QUIRK_ARM_MTK_4GB BIT(3) #define IO_PGTABLE_QUIRK_QCOM_USE_UPSTREAM_HINT BIT(4) #define IO_PGTABLE_QUIRK_PAGE_TABLE_COHERENT BIT(5) #define IO_PGTABLE_QUIRK_QSMMUV500_NON_SHAREABLE BIT(6) unsigned long quirks; unsigned long pgsize_bitmap; unsigned int ias; Loading Loading
drivers/iommu/arm-smmu.c +3 −0 Original line number Diff line number Diff line Loading @@ -1713,6 +1713,9 @@ static int arm_smmu_init_domain_context(struct iommu_domain *domain, quirks |= IO_PGTABLE_QUIRK_QCOM_USE_UPSTREAM_HINT; if (is_iommu_pt_coherent(smmu_domain)) quirks |= IO_PGTABLE_QUIRK_PAGE_TABLE_COHERENT; if ((quirks & IO_PGTABLE_QUIRK_QCOM_USE_UPSTREAM_HINT) && (smmu->model == QCOM_SMMUV500)) quirks |= IO_PGTABLE_QUIRK_QSMMUV500_NON_SHAREABLE; tlb = &arm_smmu_gather_ops; if (smmu->options & ARM_SMMU_OPT_QCOM_MMU500_ERRATA1) Loading
drivers/iommu/io-pgtable-arm.c +5 −0 Original line number Diff line number Diff line Loading @@ -1011,6 +1011,11 @@ arm_64_lpae_alloc_pgtable_s1(struct io_pgtable_cfg *cfg, void *cookie) reg = (ARM_LPAE_TCR_SH_OS << ARM_LPAE_TCR_SH0_SHIFT) | (ARM_LPAE_TCR_RGN_WBWA << ARM_LPAE_TCR_IRGN0_SHIFT) | (ARM_LPAE_TCR_RGN_WBWA << ARM_LPAE_TCR_ORGN0_SHIFT); else if ((cfg->quirks & IO_PGTABLE_QUIRK_QCOM_USE_UPSTREAM_HINT) && (cfg->quirks & IO_PGTABLE_QUIRK_QSMMUV500_NON_SHAREABLE)) reg = (ARM_LPAE_TCR_SH_NS << ARM_LPAE_TCR_SH0_SHIFT) | (ARM_LPAE_TCR_RGN_NC << ARM_LPAE_TCR_IRGN0_SHIFT) | (ARM_LPAE_TCR_RGN_WBWA << ARM_LPAE_TCR_ORGN0_SHIFT); else if (cfg->quirks & IO_PGTABLE_QUIRK_QCOM_USE_UPSTREAM_HINT) reg = (ARM_LPAE_TCR_SH_OS << ARM_LPAE_TCR_SH0_SHIFT) | (ARM_LPAE_TCR_RGN_NC << ARM_LPAE_TCR_IRGN0_SHIFT) | Loading
drivers/iommu/io-pgtable.h +7 −0 Original line number Diff line number Diff line Loading @@ -81,6 +81,12 @@ struct io_pgtable_cfg { * * IO_PGTABLE_QUIRK_PAGE_TABLE_COHERENT: Set the page table as * coherent. * * IO_PGTABLE_QUIRK_QSMMUV500_NON_SHAREABLE: * Having page tables which are non coherent, but cached in a * system cache requires SH=Non-Shareable. This applies to the * qsmmuv500 model. For data buffers SH=Non-Shareable is not * required. */ #define IO_PGTABLE_QUIRK_ARM_NS BIT(0) #define IO_PGTABLE_QUIRK_NO_PERMS BIT(1) Loading @@ -88,6 +94,7 @@ struct io_pgtable_cfg { #define IO_PGTABLE_QUIRK_ARM_MTK_4GB BIT(3) #define IO_PGTABLE_QUIRK_QCOM_USE_UPSTREAM_HINT BIT(4) #define IO_PGTABLE_QUIRK_PAGE_TABLE_COHERENT BIT(5) #define IO_PGTABLE_QUIRK_QSMMUV500_NON_SHAREABLE BIT(6) unsigned long quirks; unsigned long pgsize_bitmap; unsigned int ias; Loading