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Commit 18b078a2 authored by Kyle Yan's avatar Kyle Yan Committed by Gerrit - the friendly Code Review server
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Merge "clk: qcom: Add Display clock controller for SDM845" into msm-4.9

parents e38ff2b6 24ee2464

Documentation/devicetree/bindings/clock/qcom,dispcc.txt

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Qualcomm Technologies, Inc. Display Clock & Reset Controller Binding

----------------------------------------------------



Required properties :

- compatible : shall contain "qcom,dispcc-sdm845".

- reg : shall contain base register location and length.

- reg-names: names of registers listed in the same order as in

	     the reg property.

- #clock-cells : shall contain 1.

- #reset-cells : shall contain 1.



Optional properties :

- vdd_<rail>-supply: The logic rail supply.



Example:

	clock_dispcc: qcom,dispcc@af00000 {

		compatible = "qcom,dispcc-sdm845";

		reg = <0xaf00000 0x100000>;

		reg-names = "cc_base";

		vdd_cx-supply = <&pm8998_s9_level>;

		#clock-cells = <1>;

		#reset-cells = <1>;

	};

drivers/clk/qcom/Kconfig

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@@ -178,6 +178,15 @@ config MSM_CAMCC_SDM845 
	  Say Y if you want to support camera devices and functionality such as

	  capturing pictures.



config MSM_DISPCC_SDM845

	tristate "SDM845 Display Clock Controller"

	depends on COMMON_CLK_QCOM

	help

	  Support for the display clock controller on Qualcomm Technologies, Inc

	  sdm845 devices.

	  Say Y if you want to support display devices and functionality such as

	  splash screen.



config CLOCK_QPNP_DIV

	tristate "QPNP PMIC clkdiv driver"

	depends on COMMON_CLK_QCOM && SPMI

drivers/clk/qcom/Makefile

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@@ -28,6 +28,7 @@ obj-$(CONFIG_MSM_GCC_8960) += gcc-msm8960.o 
obj-$(CONFIG_MSM_GCC_8974) += gcc-msm8974.o

obj-$(CONFIG_MSM_GCC_8996) += gcc-msm8996.o

obj-$(CONFIG_MSM_GCC_SDM845) += gcc-sdm845.o

obj-$(CONFIG_MSM_DISPCC_SDM845) += dispcc-sdm845.o

obj-$(CONFIG_MSM_VIDEOCC_SDM845) += videocc-sdm845.o

obj-$(CONFIG_MSM_LCC_8960) += lcc-msm8960.o

obj-$(CONFIG_MSM_MMCC_8960) += mmcc-msm8960.o

drivers/clk/qcom/dispcc-sdm845.c

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File added.

Preview size limit exceeded, changes collapsed.

include/dt-bindings/clock/qcom,dispcc-sdm845.h

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/*

 * Copyright (c) 2016, The Linux Foundation. All rights reserved.

 * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -51,25 +51,16 @@ 
#define DISP_CC_MDSS_ROT_CLK_SRC				34

#define DISP_CC_MDSS_RSCC_AHB_CLK				35

#define DISP_CC_MDSS_RSCC_VSYNC_CLK				36

#define DISP_CC_MDSS_SPDM_DEBUG_CLK				37

#define DISP_CC_MDSS_SPDM_DP_CRYPTO_CLK				38

#define DISP_CC_MDSS_SPDM_DP_PIXEL1_CLK				39

#define DISP_CC_MDSS_SPDM_DP_PIXEL_CLK				40

#define DISP_CC_MDSS_SPDM_MDP_CLK				41

#define DISP_CC_MDSS_SPDM_PCLK0_CLK				42

#define DISP_CC_MDSS_SPDM_PCLK1_CLK				43

#define DISP_CC_MDSS_SPDM_ROT_CLK				44

#define DISP_CC_MDSS_VSYNC_CLK					45

#define DISP_CC_MDSS_VSYNC_CLK_SRC				46

#define DISP_CC_PLL0						47

#define DISP_CC_PLL0_OUT_EVEN					48

#define DISP_CC_PLL0_OUT_MAIN					49

#define DISP_CC_PLL0_OUT_ODD					50

#define DISP_CC_PLL0_OUT_TEST					51

#define DISP_CC_MDSS_VSYNC_CLK					37

#define DISP_CC_MDSS_VSYNC_CLK_SRC				38

#define DISP_CC_PLL0						39

#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC				40

#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC				41

#define DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC			42



#define DISP_CC_DISP_CC_MDSS_CORE_BCR				0

#define DISP_CC_DISP_CC_MDSS_GCC_CLOCKS_BCR			1

#define DISP_CC_DISP_CC_MDSS_RSCC_BCR				2

#define DISP_CC_DISP_CC_MDSS_SPDM_BCR				3

#define DISP_CC_MDSS_CORE_BCR					0

#define DISP_CC_MDSS_GCC_CLOCKS_BCR				1

#define DISP_CC_MDSS_RSCC_BCR					2

#define DISP_CC_MDSS_SPDM_BCR					3



#endif