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Commit 18a2c2c6 authored by Maciej W. Rozycki's avatar Maciej W. Rozycki Committed by Ralf Baechle
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MIPS: Correct `nofpu' non-functionality



The `cpu_has_fpu' feature flag must not be hardcoded to 1 or the `nofpu'
kernel option will be ignored.  Remove any such overrides and add a
cautionary note.  Hardcoding to 0 is fine for FPU-less platforms.

Signed-off-by: default avatarMaciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9694/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent e06b530b
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+1 −0
Original line number Diff line number Diff line
@@ -68,6 +68,7 @@
#ifndef cpu_has_octeon_cache
#define cpu_has_octeon_cache	0
#endif
/* Don't override `cpu_has_fpu' to 1 or the "nofpu" option won't work.  */
#ifndef cpu_has_fpu
#define cpu_has_fpu		(current_cpu_data.options & MIPS_CPU_FPU)
#define raw_cpu_has_fpu		(raw_current_cpu_data.options & MIPS_CPU_FPU)
+0 −1
Original line number Diff line number Diff line
@@ -14,7 +14,6 @@
#define cpu_has_3k_cache	0
#define cpu_has_4k_cache	1
#define cpu_has_tx39_cache	0
#define cpu_has_fpu		1
#define cpu_has_32fpr		1
#define cpu_has_counter		1
#define cpu_has_watch		0
+0 −1
Original line number Diff line number Diff line
@@ -15,7 +15,6 @@
/* Generic ones first.  */
#define cpu_has_tlb			1
#define cpu_has_tx39_cache		0
#define cpu_has_fpu			1
#define cpu_has_divec			0
#define cpu_has_prefetch		0
#define cpu_has_mcheck			0
+0 −1
Original line number Diff line number Diff line
@@ -16,7 +16,6 @@
#define cpu_has_tlb		1
#define cpu_has_4kex		1
#define cpu_has_4k_cache	1
#define cpu_has_fpu		1
#define cpu_has_32fpr		1
#define cpu_has_counter		1
#define cpu_has_mips16		0
+0 −1
Original line number Diff line number Diff line
@@ -26,7 +26,6 @@
/* Settings which are common for all ip32 CPUs */
#define cpu_has_tlb		1
#define cpu_has_4kex		1
#define cpu_has_fpu		1
#define cpu_has_32fpr		1
#define cpu_has_counter		1
#define cpu_has_mips16		0
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