Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 1846ac3d authored by Nick Kossifidis's avatar Nick Kossifidis Committed by John W. Linville
Browse files

ath5k: Use usleep_range where possible 



Use usleep_range where possible to reduce busy waits

Signed-off-by: default avatarNick Kossifidis <mickflemm@gmail.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent ce169aca

drivers/net/wireless/ath/ath5k/attach.c

+1 −1
Original line number Diff line number Diff line
@@ -298,7 +298,7 @@ int ath5k_hw_init(struct ath5k_hw *ah) 


		/* Reset SERDES to load new settings */

		ath5k_hw_reg_write(ah, 0x00000000, AR5K_PCIE_SERDES_RESET);

		mdelay(1);

		usleep_range(1000, 1500);

	}



	/* Get misc capabilities */

drivers/net/wireless/ath/ath5k/pci.c

+1 −1
Original line number Diff line number Diff line
@@ -98,7 +98,7 @@ ath5k_pci_eeprom_read(struct ath_common *common, u32 offset, u16 *data) 
					0xffff);

			return true;

		}

		udelay(15);

		usleep_range(15, 20);

	}



	return false;

drivers/net/wireless/ath/ath5k/phy.c

+11 −11
Original line number Diff line number Diff line
@@ -58,7 +58,7 @@ u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, enum ieee80211_band band) 
		return 0;

	}



	mdelay(2);

	usleep_range(2000, 2500);



	/* ...wait until PHY is ready and read the selected radio revision */

	ath5k_hw_reg_write(ah, 0x00001c16, AR5K_PHY(0x34));
@@ -308,9 +308,9 @@ static void ath5k_hw_wait_for_synth(struct ath5k_hw *ah, 
			delay = delay << 2;

		/* XXX: /2 on turbo ? Let's be safe

		 * for now */

		udelay(100 + delay);

		usleep_range(100 + delay, 100 + (2 * delay));

	} else {

		mdelay(1);

		usleep_range(1000, 1500);

	}

}
@@ -1083,7 +1083,7 @@ static int ath5k_hw_rf5110_channel(struct ath5k_hw *ah, 
	data = ath5k_hw_rf5110_chan2athchan(channel);

	ath5k_hw_reg_write(ah, data, AR5K_RF_BUFFER);

	ath5k_hw_reg_write(ah, 0, AR5K_RF_BUFFER_CONTROL_0);

	mdelay(1);

	usleep_range(1000, 1500);



	return 0;

}
@@ -1454,7 +1454,7 @@ static int ath5k_hw_rf5110_calibrate(struct ath5k_hw *ah, 
	beacon = ath5k_hw_reg_read(ah, AR5K_BEACON_5210);

	ath5k_hw_reg_write(ah, beacon & ~AR5K_BEACON_ENABLE, AR5K_BEACON_5210);



	mdelay(2);

	usleep_range(2000, 2500);



	/*

	 * Set the channel (with AGC turned off)
@@ -1467,7 +1467,7 @@ static int ath5k_hw_rf5110_calibrate(struct ath5k_hw *ah, 
	 * Activate PHY and wait

	 */

	ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT);

	mdelay(1);

	usleep_range(1000, 1500);



	AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
@@ -1504,7 +1504,7 @@ static int ath5k_hw_rf5110_calibrate(struct ath5k_hw *ah, 
	ath5k_hw_reg_write(ah, AR5K_PHY_RFSTG_DISABLE, AR5K_PHY_RFSTG);

	AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);



	mdelay(1);

	usleep_range(1000, 1500);



	/*

	 * Enable calibration and wait until completion
@@ -3397,7 +3397,7 @@ int ath5k_hw_phy_init(struct ath5k_hw *ah, struct ieee80211_channel *channel, 
		if (ret)

			return ret;



		mdelay(1);

		usleep_range(1000, 1500);



		/*

		 * Write RF buffer
@@ -3418,10 +3418,10 @@ int ath5k_hw_phy_init(struct ath5k_hw *ah, struct ieee80211_channel *channel, 
		}



	} else if (ah->ah_version == AR5K_AR5210) {

		mdelay(1);

		usleep_range(1000, 1500);

		/* Disable phy and wait */

		ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT);

		mdelay(1);

		usleep_range(1000, 1500);

	}



	/* Set channel on PHY */
@@ -3447,7 +3447,7 @@ int ath5k_hw_phy_init(struct ath5k_hw *ah, struct ieee80211_channel *channel, 
	for (i = 0; i <= 20; i++) {

		if (!(ath5k_hw_reg_read(ah, AR5K_PHY_ADC_TEST) & 0x10))

			break;

		udelay(200);

		usleep_range(200, 250);

	}

	ath5k_hw_reg_write(ah, phy_tst1, AR5K_PHY_TST1);

drivers/net/wireless/ath/ath5k/reset.c

+7 −7
Original line number Diff line number Diff line
@@ -357,7 +357,7 @@ static int ath5k_hw_nic_reset(struct ath5k_hw *ah, u32 val) 
	ath5k_hw_reg_write(ah, val, AR5K_RESET_CTL);



	/* Wait at least 128 PCI clocks */

	udelay(15);

	usleep_range(15, 20);



	if (ah->ah_version == AR5K_AR5210) {

		val &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_DMA
@@ -422,7 +422,7 @@ static int ath5k_hw_wisoc_reset(struct ath5k_hw *ah, u32 flags) 
	regval = __raw_readl(reg);

	__raw_writel(regval | val, reg);

	regval = __raw_readl(reg);

	udelay(100);

	usleep_range(100, 150);



	/* Bring BB/MAC out of reset */

	__raw_writel(regval & ~val, reg);
@@ -493,7 +493,7 @@ static int ath5k_hw_set_power(struct ath5k_hw *ah, enum ath5k_power_mode mode, 


		ath5k_hw_reg_write(ah, data | AR5K_SLEEP_CTL_SLE_WAKE,

							AR5K_SLEEP_CTL);

		udelay(15);

		usleep_range(15, 20);



		for (i = 200; i > 0; i--) {

			/* Check if the chip did wake up */
@@ -502,7 +502,7 @@ static int ath5k_hw_set_power(struct ath5k_hw *ah, enum ath5k_power_mode mode, 
				break;



			/* Wait a bit and retry */

			udelay(50);

			usleep_range(50, 75);

			ath5k_hw_reg_write(ah, data | AR5K_SLEEP_CTL_SLE_WAKE,

							AR5K_SLEEP_CTL);

		}
@@ -563,7 +563,7 @@ int ath5k_hw_on_hold(struct ath5k_hw *ah) 
		ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |

			AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_DMA |

			AR5K_RESET_CTL_PHY | AR5K_RESET_CTL_PCI);

			mdelay(2);

			usleep_range(2000, 2500);

	} else {

		ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |

			AR5K_RESET_CTL_BASEBAND | bus_flags);
@@ -621,7 +621,7 @@ int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, struct ieee80211_channel *channel) 
		ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |

			AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_DMA |

			AR5K_RESET_CTL_PHY | AR5K_RESET_CTL_PCI);

			mdelay(2);

			usleep_range(2000, 2500);

	} else {

		if (ath5k_get_bus_type(ah) == ATH_AHB)

			ret = ath5k_hw_wisoc_reset(ah, AR5K_RESET_CTL_PCU |
@@ -739,7 +739,7 @@ int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, struct ieee80211_channel *channel) 
		/* ...update PLL if needed */

		if (ath5k_hw_reg_read(ah, AR5K_PHY_PLL) != clock) {

			ath5k_hw_reg_write(ah, clock, AR5K_PHY_PLL);

			udelay(300);

			usleep_range(300, 350);

		}



		/* ...set the PHY operating mode */