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Commit 17eed249 authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'upstream-net26' of master.kernel.org:/pub/scm/linux/kernel/git/jgarzik/netdev-2.6

parents 4ad96d39 318a94d6

drivers/net/3c509.c

+372 −357

File changed.

Preview size limit exceeded, changes collapsed.

drivers/net/arcnet/arcnet.c

+3 −2
Original line number Diff line number Diff line
@@ -940,7 +940,7 @@ irqreturn_t arcnet_interrupt(int irq, void *dev_id) 


			/* is the RECON info empty or old? */

			if (!lp->first_recon || !lp->last_recon ||

			    jiffies - lp->last_recon > HZ * 10) {

			    time_after(jiffies, lp->last_recon + HZ * 10)) {

				if (lp->network_down)

					BUGMSG(D_NORMAL, "reconfiguration detected: cabling restored?\n");

				lp->first_recon = lp->last_recon = jiffies;
@@ -974,7 +974,8 @@ irqreturn_t arcnet_interrupt(int irq, void *dev_id) 
					lp->num_recons = 1;

				}

			}

		} else if (lp->network_down && jiffies - lp->last_recon > HZ * 10) {

		} else if (lp->network_down &&

				time_after(jiffies, lp->last_recon + HZ * 10)) {

			if (lp->network_down)

				BUGMSG(D_NORMAL, "cabling restored?\n");

			lp->first_recon = lp->last_recon = 0;

drivers/net/e1000e/82571.c

+78 −49
Original line number Diff line number Diff line 
/*******************************************************************************



  Intel PRO/1000 Linux driver

  Copyright(c) 1999 - 2007 Intel Corporation.

  Copyright(c) 1999 - 2008 Intel Corporation.



  This program is free software; you can redistribute it and/or modify it

  under the terms and conditions of the GNU General Public License,
@@ -29,6 +29,9 @@ 
/*

 * 82571EB Gigabit Ethernet Controller

 * 82571EB Gigabit Ethernet Controller (Fiber)

 * 82571EB Dual Port Gigabit Mezzanine Adapter

 * 82571EB Quad Port Gigabit Mezzanine Adapter

 * 82571PT Gigabit PT Quad Port Server ExpressModule

 * 82572EI Gigabit Ethernet Controller (Copper)

 * 82572EI Gigabit Ethernet Controller (Fiber)

 * 82572EI Gigabit Ethernet Controller
@@ -72,7 +75,7 @@ static s32 e1000_init_phy_params_82571(struct e1000_hw *hw) 
	struct e1000_phy_info *phy = &hw->phy;

	s32 ret_val;



	if (hw->media_type != e1000_media_type_copper) {

	if (hw->phy.media_type != e1000_media_type_copper) {

		phy->type = e1000_phy_none;

		return 0;

	}
@@ -150,7 +153,8 @@ static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw) 
		if (((eecd >> 15) & 0x3) == 0x3) {

			nvm->type = e1000_nvm_flash_hw;

			nvm->word_size = 2048;

			/* Autonomous Flash update bit must be cleared due

			/*

			 * Autonomous Flash update bit must be cleared due

			 * to Flash update issue.

			 */

			eecd &= ~E1000_EECD_AUPDEN;
@@ -162,7 +166,8 @@ static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw) 
		nvm->type = e1000_nvm_eeprom_spi;

		size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>

				  E1000_EECD_SIZE_EX_SHIFT);

		/* Added to a constant, "size" becomes the left-shift value

		/*

		 * Added to a constant, "size" becomes the left-shift value

		 * for setting word_size.

		 */

		size += NVM_WORD_SIZE_BASE_SHIFT;
@@ -190,16 +195,16 @@ static s32 e1000_init_mac_params_82571(struct e1000_adapter *adapter) 
	case E1000_DEV_ID_82571EB_FIBER:

	case E1000_DEV_ID_82572EI_FIBER:

	case E1000_DEV_ID_82571EB_QUAD_FIBER:

		hw->media_type = e1000_media_type_fiber;

		hw->phy.media_type = e1000_media_type_fiber;

		break;

	case E1000_DEV_ID_82571EB_SERDES:

	case E1000_DEV_ID_82572EI_SERDES:

	case E1000_DEV_ID_82571EB_SERDES_DUAL:

	case E1000_DEV_ID_82571EB_SERDES_QUAD:

		hw->media_type = e1000_media_type_internal_serdes;

		hw->phy.media_type = e1000_media_type_internal_serdes;

		break;

	default:

		hw->media_type = e1000_media_type_copper;

		hw->phy.media_type = e1000_media_type_copper;

		break;

	}
@@ -208,25 +213,28 @@ static s32 e1000_init_mac_params_82571(struct e1000_adapter *adapter) 
	/* Set rar entry count */

	mac->rar_entry_count = E1000_RAR_ENTRIES;

	/* Set if manageability features are enabled. */

	mac->arc_subsystem_valid =

		(er32(FWSM) & E1000_FWSM_MODE_MASK) ? 1 : 0;

	mac->arc_subsystem_valid = (er32(FWSM) & E1000_FWSM_MODE_MASK) ? 1 : 0;



	/* check for link */

	switch (hw->media_type) {

	switch (hw->phy.media_type) {

	case e1000_media_type_copper:

		func->setup_physical_interface = e1000_setup_copper_link_82571;

		func->check_for_link = e1000e_check_for_copper_link;

		func->get_link_up_info = e1000e_get_speed_and_duplex_copper;

		break;

	case e1000_media_type_fiber:

		func->setup_physical_interface = e1000_setup_fiber_serdes_link_82571;

		func->setup_physical_interface =

			e1000_setup_fiber_serdes_link_82571;

		func->check_for_link = e1000e_check_for_fiber_link;

		func->get_link_up_info = e1000e_get_speed_and_duplex_fiber_serdes;

		func->get_link_up_info =

			e1000e_get_speed_and_duplex_fiber_serdes;

		break;

	case e1000_media_type_internal_serdes:

		func->setup_physical_interface = e1000_setup_fiber_serdes_link_82571;

		func->setup_physical_interface =

			e1000_setup_fiber_serdes_link_82571;

		func->check_for_link = e1000e_check_for_serdes_link;

		func->get_link_up_info = e1000e_get_speed_and_duplex_fiber_serdes;

		func->get_link_up_info =

			e1000e_get_speed_and_duplex_fiber_serdes;

		break;

	default:

		return -E1000_ERR_CONFIG;
@@ -322,10 +330,12 @@ static s32 e1000_get_phy_id_82571(struct e1000_hw *hw) 
	switch (hw->mac.type) {

	case e1000_82571:

	case e1000_82572:

		/* The 82571 firmware may still be configuring the PHY.

		/*

		 * The 82571 firmware may still be configuring the PHY.

		 * In this case, we cannot access the PHY until the

		 * configuration is done.  So we explicitly set the

		 * PHY ID. */

		 * PHY ID.

		 */

		phy->id = IGP01E1000_I_PHY_ID;

		break;

	case e1000_82573:
@@ -479,8 +489,10 @@ static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw) 
	if (ret_val)

		return ret_val;



	/* If our nvm is an EEPROM, then we're done

	 * otherwise, commit the checksum to the flash NVM. */

	/*

	 * If our nvm is an EEPROM, then we're done

	 * otherwise, commit the checksum to the flash NVM.

	 */

	if (hw->nvm.type != e1000_nvm_flash_hw)

		return ret_val;
@@ -496,7 +508,8 @@ static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw) 


	/* Reset the firmware if using STM opcode. */

	if ((er32(FLOP) & 0xFF00) == E1000_STM_OPCODE) {

		/* The enabling of and the actual reset must be done

		/*

		 * The enabling of and the actual reset must be done

		 * in two write cycles.

		 */

		ew32(HICR, E1000_HICR_FW_RESET_ENABLE);
@@ -557,8 +570,10 @@ static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset, 
	u32 eewr = 0;

	s32 ret_val = 0;



	/* A check for invalid values:  offset too large, too many words,

	 * and not enough words. */

	/*

	 * A check for invalid values:  offset too large, too many words,

	 * and not enough words.

	 */

	if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||

	    (words == 0)) {

		hw_dbg(hw, "nvm parameter(s) out of bounds\n");
@@ -645,10 +660,12 @@ static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active) 
	} else {

		data &= ~IGP02E1000_PM_D0_LPLU;

		ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);

		/* LPLU and SmartSpeed are mutually exclusive.  LPLU is used

		/*

		 * LPLU and SmartSpeed are mutually exclusive.  LPLU is used

		 * during Dx states where the power conservation is most

		 * important.  During driver activity we should enable

		 * SmartSpeed, so performance is maintained. */

		 * SmartSpeed, so performance is maintained.

		 */

		if (phy->smart_speed == e1000_smart_speed_on) {

			ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,

					   &data);
@@ -693,7 +710,8 @@ static s32 e1000_reset_hw_82571(struct e1000_hw *hw) 
	s32 ret_val;

	u16 i = 0;



	/* Prevent the PCI-E bus from sticking if there is no TLP connection

	/*

	 * Prevent the PCI-E bus from sticking if there is no TLP connection

	 * on the last TLP read/write transaction when MAC is reset.

	 */

	ret_val = e1000e_disable_pcie_master(hw);
@@ -709,8 +727,10 @@ static s32 e1000_reset_hw_82571(struct e1000_hw *hw) 


	msleep(10);



	/* Must acquire the MDIO ownership before MAC reset.

	 * Ownership defaults to firmware after a reset. */

	/*

	 * Must acquire the MDIO ownership before MAC reset.

	 * Ownership defaults to firmware after a reset.

	 */

	if (hw->mac.type == e1000_82573) {

		extcnf_ctrl = er32(EXTCNF_CTRL);

		extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
@@ -747,7 +767,8 @@ static s32 e1000_reset_hw_82571(struct e1000_hw *hw) 
		/* We don't want to continue accessing MAC registers. */

		return ret_val;



	/* Phy configuration from NVM just starts after EECD_AUTO_RD is set.

	/*

	 * Phy configuration from NVM just starts after EECD_AUTO_RD is set.

	 * Need to wait for Phy configuration completion before accessing

	 * NVM and Phy.

	 */
@@ -793,7 +814,8 @@ static s32 e1000_init_hw_82571(struct e1000_hw *hw) 
	e1000e_clear_vfta(hw);



	/* Setup the receive address. */

	/* If, however, a locally administered address was assigned to the

	/*

	 * If, however, a locally administered address was assigned to the

	 * 82571, we must reserve a RAR for it to work around an issue where

	 * resetting one port will reload the MAC on the other port.

	 */
@@ -830,7 +852,8 @@ static s32 e1000_init_hw_82571(struct e1000_hw *hw) 
		ew32(GCR, reg_data);

	}



	/* Clear all of the statistics registers (clear on read).  It is

	/*

	 * Clear all of the statistics registers (clear on read).  It is

	 * important that we do this after we have tried to establish link

	 * because the symbol error count will increment wildly if there

	 * is no link.
@@ -922,7 +945,8 @@ void e1000e_clear_vfta(struct e1000_hw *hw) 


	if (hw->mac.type == e1000_82573) {

		if (hw->mng_cookie.vlan_id != 0) {

			/* The VFTA is a 4096b bit-field, each identifying

			/*

			 * The VFTA is a 4096b bit-field, each identifying

			 * a single VLAN ID.  The following operations

			 * determine which 32b entry (i.e. offset) into the

			 * array we want to set the VLAN ID (i.e. bit) of
@@ -936,7 +960,8 @@ void e1000e_clear_vfta(struct e1000_hw *hw) 
		}

	}

	for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {

		/* If the offset we want to clear is the same offset of the

		/*

		 * If the offset we want to clear is the same offset of the

		 * manageability VLAN ID, then clear all bits except that of

		 * the manageability unit.

		 */
@@ -947,7 +972,7 @@ void e1000e_clear_vfta(struct e1000_hw *hw) 
}



/**

 *  e1000_mc_addr_list_update_82571 - Update Multicast addresses

 *  e1000_update_mc_addr_list_82571 - Update Multicast addresses

 *  @hw: pointer to the HW structure

 *  @mc_addr_list: array of multicast addresses to program

 *  @mc_addr_count: number of multicast addresses to program
@@ -959,7 +984,7 @@ void e1000e_clear_vfta(struct e1000_hw *hw) 
 *  The parameter rar_count will usually be hw->mac.rar_entry_count

 *  unless there are workarounds that change this.

 **/

static void e1000_mc_addr_list_update_82571(struct e1000_hw *hw,

static void e1000_update_mc_addr_list_82571(struct e1000_hw *hw,

					    u8 *mc_addr_list,

					    u32 mc_addr_count,

					    u32 rar_used_count,
@@ -968,7 +993,7 @@ static void e1000_mc_addr_list_update_82571(struct e1000_hw *hw, 
	if (e1000e_get_laa_state_82571(hw))

		rar_count--;



	e1000e_mc_addr_list_update_generic(hw, mc_addr_list, mc_addr_count,

	e1000e_update_mc_addr_list_generic(hw, mc_addr_list, mc_addr_count,

					   rar_used_count, rar_count);

}
@@ -984,12 +1009,13 @@ static void e1000_mc_addr_list_update_82571(struct e1000_hw *hw, 
 **/

static s32 e1000_setup_link_82571(struct e1000_hw *hw)

{

	/* 82573 does not have a word in the NVM to determine

	/*

	 * 82573 does not have a word in the NVM to determine

	 * the default flow control setting, so we explicitly

	 * set it to full.

	 */

	if (hw->mac.type == e1000_82573)

		hw->mac.fc = e1000_fc_full;

		hw->fc.type = e1000_fc_full;



	return e1000e_setup_link(hw);

}
@@ -1050,14 +1076,14 @@ static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw) 
	switch (hw->mac.type) {

	case e1000_82571:

	case e1000_82572:

		/* If SerDes loopback mode is entered, there is no form

		/*

		 * If SerDes loopback mode is entered, there is no form

		 * of reset to take the adapter out of that mode.  So we

		 * have to explicitly take the adapter out of loopback

		 * mode.  This prevents drivers from twiddling their thumbs

		 * if another tool failed to take it out of loopback mode.

		 */

		ew32(SCTL,

				E1000_SCTL_DISABLE_SERDES_LOOPBACK);

		ew32(SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);

		break;

	default:

		break;
@@ -1124,7 +1150,8 @@ void e1000e_set_laa_state_82571(struct e1000_hw *hw, bool state) 


	/* If workaround is activated... */

	if (state)

		/* Hold a copy of the LAA in RAR[14] This is done so that

		/*

		 * Hold a copy of the LAA in RAR[14] This is done so that

		 * between the time RAR[0] gets clobbered and the time it

		 * gets fixed, the actual LAA is in one of the RARs and no

		 * incoming packets directed to this port are dropped.
@@ -1152,7 +1179,8 @@ static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw) 
	if (nvm->type != e1000_nvm_flash_hw)

		return 0;



	/* Check bit 4 of word 10h.  If it is 0, firmware is done updating

	/*

	 * Check bit 4 of word 10h.  If it is 0, firmware is done updating

	 * 10h-12h.  Checksum may need to be fixed.

	 */

	ret_val = e1000_read_nvm(hw, 0x10, 1, &data);
@@ -1160,7 +1188,8 @@ static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw) 
		return ret_val;



	if (!(data & 0x10)) {

		/* Read 0x23 and check bit 15.  This bit is a 1

		/*

		 * Read 0x23 and check bit 15.  This bit is a 1

		 * when the checksum has already been fixed.  If

		 * the checksum is still wrong and this bit is a

		 * 1, we need to return bad checksum.  Otherwise,
@@ -1240,7 +1269,7 @@ static struct e1000_mac_operations e82571_mac_ops = { 
	/* .get_link_up_info: media type dependent */

	.led_on			= e1000e_led_on_generic,

	.led_off		= e1000e_led_off_generic,

	.mc_addr_list_update	= e1000_mc_addr_list_update_82571,

	.update_mc_addr_list	= e1000_update_mc_addr_list_82571,

	.reset_hw		= e1000_reset_hw_82571,

	.init_hw		= e1000_init_hw_82571,

	.setup_link		= e1000_setup_link_82571,

drivers/net/e1000e/Makefile

+1 −1
Original line number Diff line number Diff line 
################################################################################

#

# Intel PRO/1000 Linux driver

# Copyright(c) 1999 - 2007 Intel Corporation.

# Copyright(c) 1999 - 2008 Intel Corporation.

#

# This program is free software; you can redistribute it and/or modify it

# under the terms and conditions of the GNU General Public License,

drivers/net/e1000e/defines.h

+58 −51
Original line number Diff line number Diff line 
/*******************************************************************************



  Intel PRO/1000 Linux driver

  Copyright(c) 1999 - 2007 Intel Corporation.

  Copyright(c) 1999 - 2008 Intel Corporation.



  This program is free software; you can redistribute it and/or modify it

  under the terms and conditions of the GNU General Public License,
@@ -120,10 +120,10 @@ 
#define E1000_MANC_ARP_EN        0x00002000 /* Enable ARP Request Filtering */

#define E1000_MANC_RCV_TCO_EN    0x00020000 /* Receive TCO Packets Enabled */

#define E1000_MANC_BLK_PHY_RST_ON_IDE   0x00040000 /* Block phy resets */

#define E1000_MANC_EN_MAC_ADDR_FILTER   0x00100000 /* Enable MAC address

						    * filtering */

#define E1000_MANC_EN_MNG2HOST   0x00200000 /* Enable MNG packets to host

					     * memory */

/* Enable MAC address filtering */

#define E1000_MANC_EN_MAC_ADDR_FILTER   0x00100000

/* Enable MNG packets to host memory */

#define E1000_MANC_EN_MNG2HOST   0x00200000



/* Receive Control */

#define E1000_RCTL_EN             0x00000002    /* enable */
@@ -135,25 +135,26 @@ 
#define E1000_RCTL_LBM_MAC        0x00000040    /* MAC loopback mode */

#define E1000_RCTL_LBM_TCVR       0x000000C0    /* tcvr loopback mode */

#define E1000_RCTL_DTYP_PS        0x00000400    /* Packet Split descriptor */

#define E1000_RCTL_RDMTS_HALF     0x00000000    /* rx desc min threshold size */

#define E1000_RCTL_RDMTS_HALF     0x00000000    /* Rx desc min threshold size */

#define E1000_RCTL_MO_SHIFT       12            /* multicast offset shift */

#define E1000_RCTL_BAM            0x00008000    /* broadcast enable */

/* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */

#define E1000_RCTL_SZ_2048        0x00000000    /* rx buffer size 2048 */

#define E1000_RCTL_SZ_1024        0x00010000    /* rx buffer size 1024 */

#define E1000_RCTL_SZ_512         0x00020000    /* rx buffer size 512 */

#define E1000_RCTL_SZ_256         0x00030000    /* rx buffer size 256 */

#define E1000_RCTL_SZ_2048        0x00000000    /* Rx buffer size 2048 */

#define E1000_RCTL_SZ_1024        0x00010000    /* Rx buffer size 1024 */

#define E1000_RCTL_SZ_512         0x00020000    /* Rx buffer size 512 */

#define E1000_RCTL_SZ_256         0x00030000    /* Rx buffer size 256 */

/* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */

#define E1000_RCTL_SZ_16384       0x00010000    /* rx buffer size 16384 */

#define E1000_RCTL_SZ_8192        0x00020000    /* rx buffer size 8192 */

#define E1000_RCTL_SZ_4096        0x00030000    /* rx buffer size 4096 */

#define E1000_RCTL_SZ_16384       0x00010000    /* Rx buffer size 16384 */

#define E1000_RCTL_SZ_8192        0x00020000    /* Rx buffer size 8192 */

#define E1000_RCTL_SZ_4096        0x00030000    /* Rx buffer size 4096 */

#define E1000_RCTL_VFE            0x00040000    /* vlan filter enable */

#define E1000_RCTL_CFIEN          0x00080000    /* canonical form enable */

#define E1000_RCTL_CFI            0x00100000    /* canonical form indicator */

#define E1000_RCTL_BSEX           0x02000000    /* Buffer size extension */

#define E1000_RCTL_SECRC          0x04000000    /* Strip Ethernet CRC */



/* Use byte values for the following shift parameters

/*

 * Use byte values for the following shift parameters

 * Usage:

 *     psrctl |= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) &

 *                  E1000_PSRCTL_BSIZE0_MASK) |
@@ -206,7 +207,8 @@ 
#define E1000_CTRL_VME      0x40000000  /* IEEE VLAN mode enable */

#define E1000_CTRL_PHY_RST  0x80000000  /* PHY Reset */



/* Bit definitions for the Management Data IO (MDIO) and Management Data

/*

 * Bit definitions for the Management Data IO (MDIO) and Management Data

 * Clock (MDC) pins in the Device Control Register.

 */
@@ -279,7 +281,7 @@ 
#define E1000_TXD_STAT_TC    0x00000004 /* Tx Underrun */



/* Transmit Control */

#define E1000_TCTL_EN     0x00000002    /* enable tx */

#define E1000_TCTL_EN     0x00000002    /* enable Tx */

#define E1000_TCTL_PSP    0x00000008    /* pad short packets */

#define E1000_TCTL_CT     0x00000ff0    /* collision threshold */

#define E1000_TCTL_COLD   0x003ff000    /* collision distance */
@@ -337,8 +339,8 @@ 
#define E1000_KABGTXD_BGSQLBIAS           0x00050000



/* PBA constants */

#define E1000_PBA_8K  0x0008    /* 8KB, default Rx allocation */

#define E1000_PBA_16K 0x0010    /* 16KB, default TX allocation */

#define E1000_PBA_8K  0x0008    /* 8KB */

#define E1000_PBA_16K 0x0010    /* 16KB */



#define E1000_PBS_16K E1000_PBA_16K
@@ -356,12 +358,13 @@ 
/* Interrupt Cause Read */

#define E1000_ICR_TXDW          0x00000001 /* Transmit desc written back */

#define E1000_ICR_LSC           0x00000004 /* Link Status Change */

#define E1000_ICR_RXSEQ         0x00000008 /* rx sequence error */

#define E1000_ICR_RXDMT0        0x00000010 /* rx desc min. threshold (0) */

#define E1000_ICR_RXT0          0x00000080 /* rx timer intr (ring 0) */

#define E1000_ICR_RXSEQ         0x00000008 /* Rx sequence error */

#define E1000_ICR_RXDMT0        0x00000010 /* Rx desc min. threshold (0) */

#define E1000_ICR_RXT0          0x00000080 /* Rx timer intr (ring 0) */

#define E1000_ICR_INT_ASSERTED  0x80000000 /* If this bit asserted, the driver should claim the interrupt */



/* This defines the bits that are set in the Interrupt Mask

/*

 * This defines the bits that are set in the Interrupt Mask

 * Set/Read Register.  Each bit is documented below:

 *   o RXT0   = Receiver Timer Interrupt (ring 0)

 *   o TXDW   = Transmit Descriptor Written Back
@@ -379,21 +382,22 @@ 
/* Interrupt Mask Set */

#define E1000_IMS_TXDW      E1000_ICR_TXDW      /* Transmit desc written back */

#define E1000_IMS_LSC       E1000_ICR_LSC       /* Link Status Change */

#define E1000_IMS_RXSEQ     E1000_ICR_RXSEQ     /* rx sequence error */

#define E1000_IMS_RXDMT0    E1000_ICR_RXDMT0    /* rx desc min. threshold */

#define E1000_IMS_RXT0      E1000_ICR_RXT0      /* rx timer intr */

#define E1000_IMS_RXSEQ     E1000_ICR_RXSEQ     /* Rx sequence error */

#define E1000_IMS_RXDMT0    E1000_ICR_RXDMT0    /* Rx desc min. threshold */

#define E1000_IMS_RXT0      E1000_ICR_RXT0      /* Rx timer intr */



/* Interrupt Cause Set */

#define E1000_ICS_LSC       E1000_ICR_LSC       /* Link Status Change */

#define E1000_ICS_RXDMT0    E1000_ICR_RXDMT0    /* rx desc min. threshold */

#define E1000_ICS_RXDMT0    E1000_ICR_RXDMT0    /* Rx desc min. threshold */



/* Transmit Descriptor Control */

#define E1000_TXDCTL_PTHRESH 0x0000003F /* TXDCTL Prefetch Threshold */

#define E1000_TXDCTL_WTHRESH 0x003F0000 /* TXDCTL Writeback Threshold */

#define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */

#define E1000_TXDCTL_MAX_TX_DESC_PREFETCH 0x0100001F /* GRAN=1, PTHRESH=31 */

#define E1000_TXDCTL_COUNT_DESC 0x00400000 /* Enable the counting of desc.

					      still to be processed. */

/* Enable the counting of desc. still to be processed. */

#define E1000_TXDCTL_COUNT_DESC 0x00400000



/* Flow Control Constants */

#define FLOW_CONTROL_ADDRESS_LOW  0x00C28001
@@ -404,7 +408,8 @@ 
#define E1000_VLAN_FILTER_TBL_SIZE 128  /* VLAN Filter Table (4096 bits) */



/* Receive Address */

/* Number of high/low register pairs in the RAR. The RAR (Receive Address

/*

 * Number of high/low register pairs in the RAR. The RAR (Receive Address

 * Registers) holds the directed and multicast addresses that we monitor.

 * Technically, we have 16 spots.  However, we reserve one of these spots

 * (RAR[15]) for our directed address used by controllers with
@@ -533,8 +538,8 @@ 
#define E1000_EECD_REQ       0x00000040 /* NVM Access Request */

#define E1000_EECD_GNT       0x00000080 /* NVM Access Grant */

#define E1000_EECD_SIZE      0x00000200 /* NVM Size (0=64 word 1=256 word) */

#define E1000_EECD_ADDR_BITS 0x00000400 /* NVM Addressing bits based on type

					 * (0-small, 1-large) */

/* NVM Addressing bits based on type (0-small, 1-large) */

#define E1000_EECD_ADDR_BITS 0x00000400

#define E1000_NVM_GRANT_ATTEMPTS   1000 /* NVM # attempts to gain grant */

#define E1000_EECD_AUTO_RD          0x00000200  /* NVM Auto Read done */

#define E1000_EECD_SIZE_EX_MASK     0x00007800  /* NVM Size */
@@ -626,7 +631,8 @@ 
#define MAX_PHY_MULTI_PAGE_REG 0xF



/* Bit definitions for valid PHY IDs. */

/* I = Integrated

/*

 * I = Integrated

 * E = External

 */

#define M88E1000_E_PHY_ID    0x01410C50
@@ -653,37 +659,37 @@ 
#define M88E1000_PSCR_MDI_MANUAL_MODE  0x0000  /* MDI Crossover Mode bits 6:5 */

					       /* Manual MDI configuration */

#define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020  /* Manual MDIX configuration */

#define M88E1000_PSCR_AUTO_X_1000T     0x0040  /* 1000BASE-T: Auto crossover,

						*  100BASE-TX/10BASE-T:

						*  MDI Mode

/* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */

#define M88E1000_PSCR_AUTO_X_1000T     0x0040

/* Auto crossover enabled all speeds */

#define M88E1000_PSCR_AUTO_X_MODE      0x0060

/*

 * 1=Enable Extended 10BASE-T distance (Lower 10BASE-T Rx Threshold)

 * 0=Normal 10BASE-T Rx Threshold

 */

#define M88E1000_PSCR_AUTO_X_MODE      0x0060  /* Auto crossover enabled

						* all speeds.

						*/

					/* 1=Enable Extended 10BASE-T distance

					 * (Lower 10BASE-T RX Threshold)

					 * 0=Normal 10BASE-T RX Threshold */

					/* 1=5-Bit interface in 100BASE-TX

					 * 0=MII interface in 100BASE-TX */

#define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */



/* M88E1000 PHY Specific Status Register */

#define M88E1000_PSSR_REV_POLARITY       0x0002 /* 1=Polarity reversed */

#define M88E1000_PSSR_DOWNSHIFT          0x0020 /* 1=Downshifted */

#define M88E1000_PSSR_MDIX               0x0040 /* 1=MDIX; 0=MDI */

#define M88E1000_PSSR_CABLE_LENGTH       0x0380 /* 0=<50M;1=50-80M;2=80-110M;

					    * 3=110-140M;4=>140M */

/* 0=<50M; 1=50-80M; 2=80-110M; 3=110-140M; 4=>140M */

#define M88E1000_PSSR_CABLE_LENGTH       0x0380

#define M88E1000_PSSR_SPEED              0xC000 /* Speed, bits 14:15 */

#define M88E1000_PSSR_1000MBS            0x8000 /* 10=1000Mbs */



#define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7



/* Number of times we will attempt to autonegotiate before downshifting if we

 * are the master */

/*

 * Number of times we will attempt to autonegotiate before downshifting if we

 * are the master

 */

#define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00

#define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X   0x0000

/* Number of times we will attempt to autonegotiate before downshifting if we

 * are the slave */

/*

 * Number of times we will attempt to autonegotiate before downshifting if we

 * are the slave

 */

#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK  0x0300

#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X    0x0100

#define M88E1000_EPSCR_TX_CLK_25      0x0070 /* 25  MHz TX_CLK */
@@ -692,7 +698,8 @@ 
#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK  0x0E00

#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X    0x0800



/* Bits...

/*

 * Bits...

 * 15-5: page

 * 4-0: register offset

 */