Loading drivers/clk/qcom/mdss/mdss-dsi-20nm-pll-util.c +2 −2 Original line number Diff line number Diff line Loading @@ -458,7 +458,7 @@ int dsi_20nm_pll_lock_status(struct mdss_pll_resources *dsi_pll_res) int pll_locked; /* poll for PLL ready status */ if (readl_poll_timeout_noirq((dsi_pll_res->pll_base + if (readl_poll_timeout_atomic((dsi_pll_res->pll_base + MMSS_DSI_PHY_PLL_RESET_SM), status, ((status & BIT(5)) > 0), Loading @@ -466,7 +466,7 @@ int dsi_20nm_pll_lock_status(struct mdss_pll_resources *dsi_pll_res) DSI_PLL_POLL_TIMEOUT_US)) { pr_debug("DSI PLL status=%x failed to Lock\n", status); pll_locked = 0; } else if (readl_poll_timeout_noirq((dsi_pll_res->pll_base + } else if (readl_poll_timeout_atomic((dsi_pll_res->pll_base + MMSS_DSI_PHY_PLL_RESET_SM), status, ((status & BIT(6)) > 0), Loading drivers/clk/qcom/mdss/mdss-dsi-pll-util.c +1 −1 Original line number Diff line number Diff line Loading @@ -239,7 +239,7 @@ int dsi_pll_lock_status(struct mdss_pll_resources *dsi_pll_res) int pll_locked; /* poll for PLL ready status */ if (readl_poll_timeout_noirq((dsi_pll_res->pll_base + if (readl_poll_timeout_atomic((dsi_pll_res->pll_base + DSI_PHY_PLL_UNIPHY_PLL_STATUS), status, ((status & BIT(0)) == 1), Loading drivers/clk/qcom/mdss/mdss-edp-pll-28hpm.c +1 −1 Original line number Diff line number Diff line Loading @@ -379,7 +379,7 @@ static int edp_pll_lock_status(struct mdss_pll_resources *edp_pll_res) } /* poll for PLL ready status */ if (readl_poll_timeout_noirq((edp_pll_res->pll_base + 0xc0), if (readl_poll_timeout_atomic((edp_pll_res->pll_base + 0xc0), status, ((status & BIT(0)) == 1), EDP_PLL_POLL_MAX_READS, EDP_PLL_POLL_TIMEOUT_US)) { Loading drivers/clk/qcom/mdss/mdss-hdmi-pll-20nm.c +2 −2 Original line number Diff line number Diff line Loading @@ -772,7 +772,7 @@ static int hdmi_20nm_pll_lock_status(struct mdss_pll_resources *io) pr_debug("%s: Waiting for PHY Ready\n", __func__); /* poll for PLL ready status */ if (!readl_poll_timeout_noirq( if (!readl_poll_timeout_atomic( (io->pll_base + QSERDES_COM_RESET_SM), status, ((status & BIT(6)) == 1), HDMI_PLL_POLL_MAX_READS, Loading @@ -785,7 +785,7 @@ static int hdmi_20nm_pll_lock_status(struct mdss_pll_resources *io) } /* poll for PHY ready status */ if (pll_locked && !readl_poll_timeout_noirq( if (pll_locked && !readl_poll_timeout_atomic( (io->phy_base + HDMI_PHY_STATUS), status, ((status & BIT(0)) == 1), HDMI_PLL_POLL_MAX_READS, Loading drivers/clk/qcom/mdss/mdss-hdmi-pll-28hpm.c +3 −3 Original line number Diff line number Diff line Loading @@ -152,7 +152,7 @@ static int hdmi_vco_enable(struct clk *c) /* poll for PLL ready status */ max_reads = 20; timeout_us = 100; if (readl_poll_timeout_noirq( if (readl_poll_timeout_atomic( (hdmi_pll_res->pll_base + HDMI_UNI_PLL_STATUS), status, ((status & BIT(0)) == 1), max_reads, timeout_us)) { pr_err("hdmi phy pll status=%x failed to Lock\n", status); Loading @@ -166,7 +166,7 @@ static int hdmi_vco_enable(struct clk *c) /* poll for PHY ready status */ max_reads = 20; timeout_us = 100; if (readl_poll_timeout_noirq( if (readl_poll_timeout_atomic( (hdmi_pll_res->phy_base + HDMI_PHY_STATUS), status, ((status & BIT(0)) == 1), max_reads, timeout_us)) { pr_err("hdmi phy status=%x failed to Lock\n", status); Loading Loading @@ -847,7 +847,7 @@ static int hdmi_pll_lock_status(struct mdss_pll_resources *hdmi_pll_res) } /* poll for PLL ready status */ if (readl_poll_timeout_noirq( if (readl_poll_timeout_atomic( (hdmi_pll_res->phy_base + HDMI_PHY_STATUS), status, ((status & BIT(0)) == 1), HDMI_PLL_POLL_MAX_READS, Loading Loading
drivers/clk/qcom/mdss/mdss-dsi-20nm-pll-util.c +2 −2 Original line number Diff line number Diff line Loading @@ -458,7 +458,7 @@ int dsi_20nm_pll_lock_status(struct mdss_pll_resources *dsi_pll_res) int pll_locked; /* poll for PLL ready status */ if (readl_poll_timeout_noirq((dsi_pll_res->pll_base + if (readl_poll_timeout_atomic((dsi_pll_res->pll_base + MMSS_DSI_PHY_PLL_RESET_SM), status, ((status & BIT(5)) > 0), Loading @@ -466,7 +466,7 @@ int dsi_20nm_pll_lock_status(struct mdss_pll_resources *dsi_pll_res) DSI_PLL_POLL_TIMEOUT_US)) { pr_debug("DSI PLL status=%x failed to Lock\n", status); pll_locked = 0; } else if (readl_poll_timeout_noirq((dsi_pll_res->pll_base + } else if (readl_poll_timeout_atomic((dsi_pll_res->pll_base + MMSS_DSI_PHY_PLL_RESET_SM), status, ((status & BIT(6)) > 0), Loading
drivers/clk/qcom/mdss/mdss-dsi-pll-util.c +1 −1 Original line number Diff line number Diff line Loading @@ -239,7 +239,7 @@ int dsi_pll_lock_status(struct mdss_pll_resources *dsi_pll_res) int pll_locked; /* poll for PLL ready status */ if (readl_poll_timeout_noirq((dsi_pll_res->pll_base + if (readl_poll_timeout_atomic((dsi_pll_res->pll_base + DSI_PHY_PLL_UNIPHY_PLL_STATUS), status, ((status & BIT(0)) == 1), Loading
drivers/clk/qcom/mdss/mdss-edp-pll-28hpm.c +1 −1 Original line number Diff line number Diff line Loading @@ -379,7 +379,7 @@ static int edp_pll_lock_status(struct mdss_pll_resources *edp_pll_res) } /* poll for PLL ready status */ if (readl_poll_timeout_noirq((edp_pll_res->pll_base + 0xc0), if (readl_poll_timeout_atomic((edp_pll_res->pll_base + 0xc0), status, ((status & BIT(0)) == 1), EDP_PLL_POLL_MAX_READS, EDP_PLL_POLL_TIMEOUT_US)) { Loading
drivers/clk/qcom/mdss/mdss-hdmi-pll-20nm.c +2 −2 Original line number Diff line number Diff line Loading @@ -772,7 +772,7 @@ static int hdmi_20nm_pll_lock_status(struct mdss_pll_resources *io) pr_debug("%s: Waiting for PHY Ready\n", __func__); /* poll for PLL ready status */ if (!readl_poll_timeout_noirq( if (!readl_poll_timeout_atomic( (io->pll_base + QSERDES_COM_RESET_SM), status, ((status & BIT(6)) == 1), HDMI_PLL_POLL_MAX_READS, Loading @@ -785,7 +785,7 @@ static int hdmi_20nm_pll_lock_status(struct mdss_pll_resources *io) } /* poll for PHY ready status */ if (pll_locked && !readl_poll_timeout_noirq( if (pll_locked && !readl_poll_timeout_atomic( (io->phy_base + HDMI_PHY_STATUS), status, ((status & BIT(0)) == 1), HDMI_PLL_POLL_MAX_READS, Loading
drivers/clk/qcom/mdss/mdss-hdmi-pll-28hpm.c +3 −3 Original line number Diff line number Diff line Loading @@ -152,7 +152,7 @@ static int hdmi_vco_enable(struct clk *c) /* poll for PLL ready status */ max_reads = 20; timeout_us = 100; if (readl_poll_timeout_noirq( if (readl_poll_timeout_atomic( (hdmi_pll_res->pll_base + HDMI_UNI_PLL_STATUS), status, ((status & BIT(0)) == 1), max_reads, timeout_us)) { pr_err("hdmi phy pll status=%x failed to Lock\n", status); Loading @@ -166,7 +166,7 @@ static int hdmi_vco_enable(struct clk *c) /* poll for PHY ready status */ max_reads = 20; timeout_us = 100; if (readl_poll_timeout_noirq( if (readl_poll_timeout_atomic( (hdmi_pll_res->phy_base + HDMI_PHY_STATUS), status, ((status & BIT(0)) == 1), max_reads, timeout_us)) { pr_err("hdmi phy status=%x failed to Lock\n", status); Loading Loading @@ -847,7 +847,7 @@ static int hdmi_pll_lock_status(struct mdss_pll_resources *hdmi_pll_res) } /* poll for PLL ready status */ if (readl_poll_timeout_noirq( if (readl_poll_timeout_atomic( (hdmi_pll_res->phy_base + HDMI_PHY_STATUS), status, ((status & BIT(0)) == 1), HDMI_PLL_POLL_MAX_READS, Loading